Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor-single electron transistor integrated circuits

For the first time, the impact of energy quantisation in single electron transistor (SET) island on the performance of hybrid complementary metal oxide semiconductor (CMOS)-SET transistor circuits has been studied. It has been shown through simple analytical models that energy quantisation primarily increases the Coulomb Blockade area and Coulomb Blockade oscillation periodicity of the SET device and thus influences the performance of hybrid CMOS-SET circuits. A novel computer aided design (CAD) framework has been developed for hybrid CMOS-SET co-simulation, which uses Monte Carlo (MC) simulator for SET devices along with conventional SPICE for metal oxide semiconductor devices. Using this co-simulation framework, the effects of energy quantisation have been studied for some hybrid circuits, namely, SETMOS, multiband voltage filter and multiple valued logic circuits. Although energy quantisation immensely deteriorates the performance of the hybrid circuits, it has been shown that the performance degradation because of energy quantisation can be compensated by properly tuning the bias current of the current-biased SET devices within the hybrid CMOS-SET circuits. Although this study is primarily done by exhaustive MC simulation, effort has also been put to develop first-order compact model for SET that includes energy quantisation effects. Finally, it has been demonstrated that one can predict the SET behaviour under energy quantisation with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

Complementary metal-oxide-semiconductor-compatible and self-aligned catalyst formation for carbon nanotube synthesis and interconnect fabrication

We have for the first time developed a self-aligned metal catalyst formation process using fully CMOS (complementary metal-oxide-semiconductor) compatible materials and techniques, for the synthesis of aligned carbon nanotubes (CNTs). By employing an electrically conductive cobalt disilicide (CoSi 2) layer as the starting material, a reactive ion etch (RIE) treatment and a hydrogen reduction step are used to transform the CoSi 2 surface into cobalt (Co) nanoparticles that are active to catalyze aligned CNT growth. Ohmic contacts between the conductive substrate and the CNTs are obtained. The process developed in this study can be applied to form metal nanoparticles in regions that cannot be patterned using conventional catalyst deposition methods, for example at the bottom of deep holes or on vertical surfaces. This catalyst formation method is crucially important for the fabrication of vertical and horizontal interconnect devices based on CNTs. © 2012 American Institute of Physics.

Photodetection with gate-controlled lateral BJTs from standard CMOS technology

The silicon-based gate-controlled lateral bipolar junction transistor (BJT) is a controllable four-terminal photodetector with very high responsivity at low-light intensities. It is a hybrid device composed of a MOSFET, a lateral BJT, and a vertical BJT. Using sufficient gate bias to operate the MOS transistor in inversion mode, the photodetector allows for increasing the photocurrent gain by 106 at low light intensities when the base-emitter voltage is smaller than 0.4 V, and BJT is off. Two operation modes, with constant voltage bias between gate and emitter/source terminals and between gate and base/body terminals, allow for tuning the photoresponse from sublinear to slightly above linear, satisfying the application requirements for wide dynamic range, high-contrast, or linear imaging. MOSFETs from a standard 0.18-μm triple-well complementary-metal oxide semiconductor technology with a width to length ratio of 8 μm /2 μm and a total area of ∼ 500μm2 are used. When using this area, the responsivities are 16-20 kA/W. © 2001-2012 IEEE.

Bright-field and fluorescence chip-scale microscopy for biological imaging

Optical microscopy is an essential tool in biological science and one of the gold standards for medical examinations. Miniaturization of microscopes can be a crucial stepping stone towards realizing compact, cost-effective and portable platforms for biomedical research and healthcare. This thesis reports on implementations of bright-field and fluorescence chip-scale microscopes for a variety of biological imaging applications. The term “chip-scale microscopy” refers to lensless imaging techniques realized in the form of mass-producible semiconductor devices, which transforms the fundamental design of optical microscopes.

Our strategy for chip-scale microscopy involves utilization of low-cost Complementary metal Oxide Semiconductor (CMOS) image sensors, computational image processing and micro-fabricated structural components. First, the sub-pixel resolving optofluidic microscope (SROFM), will be presented, which combines microfluidics and pixel super-resolution image reconstruction to perform high-throughput imaging of fluidic samples, such as blood cells. We discuss design parameters and construction of the device, as well as the resulting images and the resolution of the device, which was 0.66 µm at the highest acuity. The potential applications of SROFM for clinical diagnosis of malaria in the resource-limited settings is discussed.

Next, the implementations of ePetri, a self-imaging Petri dish platform with microscopy resolution, are presented. Here, we simply place the sample of interest on the surface of the image sensor and capture the direct shadow images under the illumination. By taking advantage of the inherent motion of the microorganisms, we achieve high resolution (~1 µm) imaging and long term culture of motile microorganisms over ultra large field-of-view (5.7 mm × 4.4 mm) in a specialized ePetri platform. We apply the pixel super-resolution reconstruction to a set of low-resolution shadow images of the microorganisms as they move across the sensing area of an image sensor chip and render an improved resolution image. We perform longitudinal study of Euglena gracilis cultured in an ePetri platform and image based analysis on the motion and morphology of the cells. The ePetri device for imaging non-motile cells are also demonstrated, by using the sweeping illumination of a light emitting diode (LED) matrix for pixel super-resolution reconstruction of sub-pixel shifted shadow images. Using this prototype device, we demonstrate the detection of waterborne parasites for the effective diagnosis of enteric parasite infection in resource-limited settings.

Then, we demonstrate the adaptation of a smartphone’s camera to function as a compact lensless microscope, which uses ambient illumination as its light source and does not require the incorporation of a dedicated light source. The method is also based on the image reconstruction with sweeping illumination technique, where the sequence of images are captured while the user is manually tilting the device around any ambient light source, such as the sun or a lamp. Image acquisition and reconstruction is performed on the device using a custom-built android application, constructing a stand-alone imaging device for field applications. We discuss the construction of the device using a commercial smartphone and demonstrate the imaging capabilities of our system.

Finally, we report on the implementation of fluorescence chip-scale microscope, based on a silo-filter structure fabricated on the pixel array of a CMOS image sensor. The extruded pixel design with metal walls between neighboring pixels successfully guides fluorescence emission through the thick absorptive filter to the photodiode layer of a pixel. Our silo-filter CMOS image sensor prototype achieves 13-µm resolution for fluorescence imaging over a wide field-of-view (4.8 mm × 4.4 mm). Here, we demonstrate bright-field and fluorescence longitudinal imaging of living cells in a compact, low-cost configuration.

Characterisation of humidity dependence of a metal oxide semiconductor (MOS) sensor array using Partial Least Squares (PLS)

Metal oxide semiconductor (MOS) sensors are a class of chemical sensor that have potential for being a practical core sensor module for an electronic nose system in various environmental monitoring applications. However, the responses of these sensors may be affected by changes in humidity and this must be taken into consideration when developing calibration models. This paper characterises the humidity dependence of a sensor array which consists of 12 MOS sensors. The results were used to develop calibration models using partial least squares. Effects of humidity on the response of the sensor array and predictive ability of partial least squares are discussed. It is shown that partial least squares can provide proper calibration models to compensate for effects caused by changes in humidity.

Characterisation of humidity dependence of a metal oxide semiconductor sensor array using partial least squares

Metal oxide semiconductor (MOS) sensors are a class of chemical sensors that have potential for being a practical core sensor module for an electronic nose system in various environmental monitoring applications. However, the responses of these sensors may be affected by changes in humidity and this must be taken into consideration when developing calibration models. This paper characterises the humidity dependence of a sensor array which consists of 12 MOS sensors. The results were used to develop calibration models using partial least squares (PLS). Effects of humidity on the response of the sensor array and predictive ability of partial least squares are discussed. It is shown that partial least squares can provide proper calibration models to compensate for effects caused by changes in humidity. Special Issue: Selected Paper from the 12th International Symposium on Olfaction and Electronic Noses - ISOEN 2007, International Symposium on Olfaction and Electronic Noses.

A thermopile based SOI CMOS MEMS wall shear stress sensor

In this paper we present for the first time, a novel silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) MEMS thermal wall shear stress sensor based on a tungsten hot-film and three thermopiles. These devices have been fabricated using a commercial 1 μm SOI-CMOS process followed by a deep reactive ion etch (DRIE) back-etch step to create silicon oxide membranes under the hot-film for effective thermal isolation. The sensors show an excellent repeatability of electro-thermal characteristics and can be used to measure wall shear stress in both constant current anemometric as well as calorimetric modes. The sensors have been calibrated for wall shear stress measurement of air in the range of 0-0.48 Pa using a suction type, 2-D flow wind tunnel. The calibration results show that the sensors have a higher sensitivity (up to four times) in calorimetric mode compared to anemometric mode for wall shear stress lower than 0.3 Pa. © 2013 IEEE.

SOI CMOS integrated zinc oxide nanowire for toluene detection

The paper reports on the in-situ growth of zinc oxide nanowires (ZnONWs) on a complementary metal oxide semiconductor (CMOS) substrate, and their performance as a sensing element for ppm (parts per million) levels of toluene vapour in 3000 ppm humid air. Zinc oxide NWs were grown using a low temperature (only 90°C) hydrothermal method. The ZnONWs were first characterised both electrically and through scanning electron microscopy. Then the response of the on-chip ZnONWs to different concentrations of toluene (400-2600ppm) was observed in air at 300°C. Finally, their gas sensitivity was determined and found to lie between 0.1% and 0.3% per ppm. © 2013 IEEE.

Impedance‐frequency characteristics of metal‐oxide‐semiconductor structures on polycrystalline silicon

This paper reports the variations in impedance with frequency of metal‐oxide‐semiconductor (MOS) structures on polycrystalline silicon. The origin of these impedance‐frequency characteristics are qualitatively explained. These characteristics indicate that the MOS structure on polycrystalline silicon can be exploited to realize voltage controlled filters.

Effect of gate-drain/source overlap on the noise in 90 nm N-channel metal oxide semiconductor field effect transistors

In this paper, we have studied the effect of gate-drain/source overlap (LOV) on the drain channel noise and induced gate current noise (SIg) in 90 nm N-channel metal oxide semiconductor field effect transistors using process and device simulations. As the change in overlap affects the gate tunneling leakage current, its effect on shot noise component of SIg has been taken into consideration. It has been shown that “control over LOV” allows us to get better noise performance from the device, i.e., it allows us to reduce noise figure, for a given leakage current constraint. LOV in the range of 0–10 nm is recommended for the 90 nm gate length transistors, in order to get the best performance in radio frequency applications.

Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

We report on the threshold voltage modeling of ultra-thin (1 nm-5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (V th) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φ c) saturates to Φ c (s a t), and analyze the effects of oxide thickness (t ox) and substrate doping (N A) variations on V th. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed V t h definition, electrically corresponds to a condition where the inversion layer capacitance (C i n v) is equal to the oxide capacitance (C o x) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria C i n v C o x is proposed to compute Φ c (s a t), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (x) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film. © 2012 American Institute of Physics.

Analysis of size quantization and temperature effects on the threshold voltage of thin silicon film double-gate metal-oxide-semiconductor field-effect transistor (MOSFET)

In this paper, we analyze the combined effects of size quantization and device temperature variations (T = 50K to 400 K) on the intrinsic carrier concentration (n(i)), electron concentration (n) and thereby on the threshold voltage (V-th) for thin silicon film (t(si) = 1 nm to 10 nm) based fully-depleted Double-Gate Silicon-on-Insulator MOSFETs. The threshold voltage (V-th) is defined as the gate voltage (V-g) at which the potential at the center of the channel (Phi(c)) begins to saturate (Phi(c) = Phi(c(sat))). It is shown that in the strong quantum confinement regime (t(si) <= 3nm), the effects of size quantization far over-ride the effects of temperature variations on the total change in band-gap (Delta E-g(eff)), intrinsic carrier concentration (n(i)), electron concentration (n), Phi(c(sat)) and the threshold voltage (V-th). On the other hand, for t(si) >= 4 nm, it is shown that size quantization effects recede with increasing t(si), while the effects of temperature variations become increasingly significant. Through detailed analysis, a physical model for the threshold voltage is presented both for the undoped and doped cases valid over a wide-range of device temperatures, silicon film thicknesses and substrate doping densities. Both in the undoped and doped cases, it is shown that the threshold voltage strongly depends on the channel charge density and that it is independent of incomplete ionization effects, at lower device temperatures. The results are compared with the published work available in literature, and it is shown that the present approach incorporates quantization and temperature effects over the entire temperature range. We also present an analytical model for V-th as a function of device temperature (T). (C) 2013 AIP Publishing LLC.

Negative differential resistance and effect of defects and deformations in MoS2 armchair nanoribbon metal-oxide-semiconductor field effect transistor

In this work, we present a study on the negative differential resistance (NDR) behavior and the impact of various deformations (like ripple, twist, wrap) and defects like vacancies and edge roughness on the electronic properties of short-channel MoS2 armchair nanoribbon MOSFETs. The effect of deformation (3 degrees-7 degrees twist or wrap and 0.3-0.7 angstrom ripple amplitude) and defects on a 10 nm MoS2 ANR FET is evaluated by the density functional tight binding theory and the non-equilibrium Green's function approach. We study the channel density of states, transmission spectra, and the I-D-V-D characteristics of such devices under the varying conditions, with focus on the NDR behavior. Our results show significant change in the NDR peak to valley ratio and the NDR window with such minor intrinsic deformations, especially with the ripple. (C) 2013 AIP Publishing LLC.