Voltage regulator modeling for the three-phase power flow in distribution networks

In this paper a three-phase power flow for electrical distribution systems considering different models of voltage regulators is presented. A voltage regulator (VR) is an equipment that maintains the voltage level in a predefined value in a distribution line in spite of the load variations within its nominal power. Three different types of connections are analyzed: 1) wye-connected regulators, 2) open delta-connected regulators and 3) closed delta-connected regulators. To calculate the power flow, the three-phase backward/forward sweep algorithm is used. The methodology is tested on the IEEE 34 bus distribution system. ©2008 IEEE.

Dynamic voltage restorer development and testing

The growing use of sensitive loads in the electric power system, especially in industrial applications, increases voltage sags related production losses considerably, stimulating a demand for power electronics' based solutions to mitigate the effects of such problems. This paper shows the implementation and some industrial certification tests of a power equipment prototype designed to correct sags and swells, a dynamic voltage restorer, which is one of the many possible solutions for voltage sags and swells problems Experimental results of a 75kVA prototype are shown both in laboratory and full load conditions, in a certification institution (IEE-USP). © 2011 IEEE.

Technology assessment for power quality mitigation devices - Micro-DVR case study

This work presents a case study on technology assessment for power quality devices. A system compatibility test protocol for power quality mitigation devices was developed in order to evaluate the functionality of three-phase voltage restoration devices. In order to case test this test protocol, a development platform with reduced power for DVR (Dynamic Voltage Restorer), the Micro-DVR, was tested, and results were discussed based on voltage disturbances standards. ©2008 IEEE.

Optimal allocation of distributed generators providing reactive power support ancillary service

Problems as voltage increase at the end of a feeder, demand supply unbalance in a fault condition, power quality decline, increase of power losses, and reduction of reliability levels may occur if Distributed Generators (DGs) are not properly allocated. For this reason, researchers have been employed several solution techniques to solve the problem of optimal allocation of DGs. This work is focused on the ancillary service of reactive power support provided by DGs. The main objective is to price this service by determining the costs in which a DG incurs when it loses sales opportunity of active power, i.e, by determining the Loss of Opportunity Costs (LOC). The LOC will be determined for different allocation alternatives of DGs as a result of a multi-objective optimization process, aiming the minimization of losses in the lines of the system and costs of active power generation from DGs, and the maximization of the static voltage stability margin of the system. The effectiveness of the proposed methodology in improving the goals outlined was demonstrated using the IEEE 34 bus distribution test feeder with two DGs cosidered to be allocated. © 2011 IEEE.

Pricing of reactive power support provided by distributed generators in transmission systems

Distributed Generation, microgrid technologies, two-way communication systems, and demand response programs are issues that are being studied in recent years within the concept of smart grids. At some level of enough penetration, the Distributed Generators (DGs) can provide benefits for sub-transmission and transmission systems through the so-called ancillary services. This work is focused on the ancillary service of reactive power support provided by DGs, specifically Wind Turbine Generators (WTGs), with high level of impact on transmission systems. The main objective of this work is to propose an optimization methodology to price this service by determining the costs in which a DG incurs when it loses sales opportunity of active power, i.e, by determining the Loss of Opportunity Costs (LOC). LOC occur when more reactive power is required than available, and the active power generation has to be reduced in order to increase the reactive power capacity. In the optimization process, three objectives are considered: active power generation costs of DGs, voltage stability margin of the system, and losses in the lines of the network. Uncertainties of WTGs are reduced solving multi-objective optimal power flows in multiple probabilistic scenarios constructed by Monte Carlo simulations, and modeling the time series associated with the active power generation of each WTG via Fuzzy Logic and Markov Chains. The proposed methodology was tested using the IEEE 14 bus test system with two WTGs installed. © 2011 IEEE.

A Voltage Limiter Circuit for Indoor Light Energy Harvesting Applications

A voltage limiter circuit for indoor light energy harvesting applications is presented. This circuit is a part of a bigger system, whose function is to harvest indoor light energy, process it and store it, so that it can be used at a later time. This processing consists on maximum power point tracking (MPPT) and stepping-up, of the voltage from the photovoltaic (PV) harvester cell. The circuit here described, ensures that even under strong illumination, the generated voltage will not exceed the limit allowed by the technology, avoiding the degradation, or destruction, of the integrated die. A prototype of the limiter circuit was designed in a 130 nm CMOS technology. The layout of the circuit has a total area of 23414 mu m(2). Simulation results, using Spectre, are presented.

Projecto de um conversor redutor CC-CC comutado para SoC

A evolução da tecnologia CMOS tem possibilitado uma maior densidade de integração de circuitos tornando possível o aumento da complexidade dos sistemas. No entanto, a integração de circuitos de gestão de potência continua ainda em estudo devido à dificuldade de integrar todos os componentes. Esta solução apresenta elevadas vantagens, especialmente em aplicações electrónicas portáteis alimentadas a baterias, onde a autonomia é das principais características. No âmbito dos conversores redutores existem várias topologias de circuitos que são estudadas na área de integração. Na categoria dos conversores lineares utiliza-se o LDO (Low Dropout Regulator), apresentando no entanto baixa eficiência para relações de conversão elevadas. Os conversores comutados são elaborados através do recurso a circuitos de comutação abrupta, em que a eficiência deste tipo de conversores não depende do rácio de transformação entre a tensão de entrada e a de saída. A diminuição física dos processos CMOS tem como consequência a redução da tensão máxima que os transístores suportam, impondo o estudo de soluções tolerantes a “altatensão”, com o intuito de manter compatibilidade com tensões superiores que existam na placa onde o circuito é incluído. Os sistemas de gestão de energia são os primeiros a acompanhar esta evolução, tendo de estar aptos a fornecer a tensão que os restantes circuitos requerem. Neste trabalho é abordada uma metodologia de projecto para conversores redutores CCCC comutados em tecnologia CMOS, tendo-se maximizado a frequência com vista à integração dos componentes de filtragem em circuito integrado. A metodologia incide sobre a optimização das perdas totais inerentes à comutação e condução, dos transístores de potência e respectivos circuitos auxiliares. É apresentada uma nova metodologia para o desenvolvimento de conversores tolerantes a “alta-tensão”.

Analogisen tunnisteanalyysin käyttö korjauspalveluissa mikropiirien ylijännitteestä aiheutuneiden vaurioiden paikantamisen

Korjauspalveluissa aikaa vieviä tapauksia ovat mikropiirien vaikeasti paikannettavat viat. Tällaista vianetsintää varten yrityksemme oli ostanut Polar Fault Locator 780 –mittalaitteen, jolla voidaan mitata mikropiirien toimintaa käyttämällä analogista tunnisteanalyysiä. Diplomityön tavoitteena oli selvittää, miten mittaustapaa voidaan käyttää korjauspalveluissa. Tutkintaa lähestyttiin joidenkin tyypillisten komponenttien näkökulmasta, mutta pääpaino oli mikropiireissä. Joitain mikropiirejä vaurioitettiin tahallisesti, jolloin mittaustulokset uusittiin ja tutkittiin miten vaurioituminen näkyy mittaustuloksissa. Tutkimusmenetelmänä oli kirjallisuus ja empiirinen kokeellisuus. Diplomityön tuloksena oli, että tätä mittaustapaa käyttämällä mikropiirien kuntoa voidaan tutkia. Ongelmiksi osoittautuivat alkuperäinen oletus mittalaitteen tuloksien tulkinnasta ja taustamateriaalin heikko saatavuus. Täten mittalaite parhaiten soveltuu tilanteisiin, joissa sen antamia tuloksia verrataan suoraan toisen toimivaksi tunnetun yksikön mittaustuloksiin. Vaurioitettaessa komponenteissa oli kuitenkin havaittavissa selvä poikkeavuus.

Low-voltage low-power CMOS analogue circuits for Gaussian and uniform noise generation

IEEE International Symposium on Circuits and Systems, MAY 25-28, 2003, Bangkok, Thailand. (ISI Web of Science)

Feasibility of Electronic Tap-Changing Stabilizers for Medium Voltage Lines-Precedents and New Configurations

Thyristor-based onload tap-changing ac voltage stabilizers are cheap and robust. They have replaced most mechanical tap-changers in low voltage applications from 300 VA to 300 M. Nevertheless, this replacement hardily applies to tap-changers associated to transformers feeding medium-voltage lines (typically 69 kV primary, 34.5 kV line, 10 MVA) which need periodical maintenance of contacts and oil. The Electric Power Research Institute (EPRI) has studied the feasibility of this replacement. It detected economical problems derived from the need for series association of thyristors to manage the high voltages involved, and from the current overload developed under line fault. The paper reviews the configurations used in that field and proposes new solutions, using a compensating transformer in the main circuit and multi-winding coils in the commutating circuit, with reduced overload effect and no series association of thyristors, drastically decreasing their number and rating. The stabilizer can be installed at any point of the line and the electronic circuit can be fixed to ground. Subsequent works study and synthesize several commutating circuits in detail.

A new method of threshold voltage extraction via MOSFET gate-to-substrate capacitance measurement

A new method to extract MOSFET's threshold voltage VT by measurement of the gate-to-substrate capacitance C-gb of the transistor is presented. Unlike existing extraction methods based on I-V data, the measurement of C-gb does not require de drain current to now between drain and source thus eliminating the effects of source and drain series resistance R-S/D, and at the same time, retains a symmetrical potential profile across the channel. Experimental and simulation results on devices with different sizes are presented to justify the proposed method.

Solid-state Marx based two-switch voltage modulator for the On-Line Isotope Mass Separator accelerator at the European Organization for Nuclear Research

A new circuit topology is proposed to replace the actual pulse transformer and thyratron based resonant modulator that supplies the 60 kV target potential for the ion acceleration of the On-Line Isotope Mass Separator accelerator, the stability of which is critical for the mass resolution downstream separator, at the European Organization for Nuclear Research. The improved modulator uses two solid-state switches working together, each one based on the Marx generator concept, operating as series and parallel switches, reducing the stress on the series stacked semiconductors, and also as auxiliary pulse generator in order to fulfill the target requirements. Preliminary results of a 10 kV prototype, using 1200 V insulated gate bipolar transistors and capacitors in the solid-state Marx circuits, ten stages each, with an electrical equivalent circuit of the target, are presented, demonstrating both the improved voltage stability and pulse flexibility potential wanted for this new modulator.

Repetitive Solid State Pulse Modulator Based on a DC Voltage Multiplier

A newly developed solid-state repetitive high-voltage (HV) pulse modulator topology created from the mature concept of the d.c. voltage multiplier (VM) is described. The proposed circuit is based in a voltage multiplier type circuit, where a number of d.c. capacitors share a common connection with different voltage rating in each one. Hence, besides the standard VM rectifier and coupling diodes, two solid-state on/off switches are used, in each stage, to switch from the typical charging VM mode to a pulse mode with the d.c. capacitors connected in series with the load. Due to the on/off semiconductor configuration, in half-bridge structures, the maximum voltage blocked by each one is the d.c. capacitor voltage in each stage. A 2 kV prototype is described and the results are compared with PSPICE simulations.

A DC-DC Step-Up mu-Power Converter for Energy Harvesting Applications, Using Maximum Power PointTracking, Based on Fractional Open Circuit Voltage

A DC-DC step-up micro power converter for solar energy harvesting applications is presented. The circuit is based on a switched-capacitorvoltage tripler architecture with MOSFET capacitors, which results in an, area approximately eight times smaller than using MiM capacitors for the 0.131mu m CMOS technology. In order to compensate for the loss of efficiency, due to the larger parasitic capacitances, a charge reutilization scheme is employed. The circuit is self-clocked, using a phase controller designed specifically to work with an amorphous silicon solar cell, in order to obtain themaximum available power from the cell. This will be done by tracking its maximum power point (MPPT) using the fractional open circuit voltage method. Electrical simulations of the circuit, together with an equivalent electrical model of an amorphous silicon solar cell, show that the circuit can deliver apower of 1132 mu W to the load, corresponding to a maximum efficiency of 66.81%.