Scalable Unified Transform Architecture for Advanced Video Coding Embedded Systems

A novel high throughput and scalable unified architecture for the computation of the transform operations in video codecs for advanced standards is presented in this paper. This structure can be used as a hardware accelerator in modern embedded systems to efficiently compute all the two-dimensional 4 x 4 and 2 x 2 transforms of the H.264/AVC standard. Moreover, its highly flexible design and hardware efficiency allows it to be easily scaled in terms of performance and hardware cost to meet the specific requirements of any given video coding application. Experimental results obtained using a Xilinx Virtex-5 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which presents a throughput per unit of area relatively higher than other similar recently published designs targeting the H.264/AVC standard. Such results also showed that, when integrated in a multi-core embedded system, this architecture provides speedup factors of about 120x concerning pure software implementations of the transform algorithms, therefore allowing the computation, in real-time, of all the above mentioned transforms for Ultra High Definition Video (UHDV) sequences (4,320 x 7,680 @ 30 fps).

Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs

A unified architecture for fast and efficient computation of the set of two-dimensional (2-D) transforms adopted by the most recent state-of-the-art digital video standards is presented in this paper. Contrasting to other designs with similar functionality, the presented architecture is supported on a scalable, modular and completely configurable processing structure. This flexible structure not only allows to easily reconfigure the architecture to support different transform kernels, but it also permits its resizing to efficiently support transforms of different orders (e. g. order-4, order-8, order-16 and order-32). Consequently, not only is it highly suitable to realize high-performance multi-standard transform cores, but it also offers highly efficient implementations of specialized processing structures addressing only a reduced subset of transforms that are used by a specific video standard. The experimental results that were obtained by prototyping several configurations of this processing structure in a Xilinx Virtex-7 FPGA show the superior performance and hardware efficiency levels provided by the proposed unified architecture for the implementation of transform cores for the Advanced Video Coding (AVC), Audio Video coding Standard (AVS), VC-1 and High Efficiency Video Coding (HEVC) standards. In addition, such results also demonstrate the ability of this processing structure to realize multi-standard transform cores supporting all the standards mentioned above and that are capable of processing the 8k Ultra High Definition Television (UHDTV) video format (7,680 x 4,320 at 30 fps) in real time.

High Performance Multi-Standard Architecture for DCT Computation in H.264/AVC High Profile and HEVC Codecs

A new high performance architecture for the computation of all the DCT operations adopted in the H.264/AVC and HEVC standards is proposed in this paper. Contrasting to other dedicated transform cores, the presented multi-standard transform architecture is supported on a completely configurable, scalable and unified structure, that is able to compute not only the forward and the inverse 8×8 and 4×4 integer DCTs and the 4×4 and 2×2 Hadamard transforms defined in the H.264/AVC standard, but also the 4×4, 8×8, 16×16 and 32×32 integer transforms adopted in HEVC. Experimental results obtained using a Xilinx Virtex-7 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which outperforms its more prominent related designs by at least 1.8 times. When integrated in a multi-core embedded system, this architecture allows the computation, in real-time, of all the transforms mentioned above for resolutions as high as the 8k Ultra High Definition Television (UHDTV) (7680×4320 @ 30fps).

Common architecture for discrete wavelet transform analysis and synthesis with sequential and constant processing elements

This paper adresses the problem on processing biological data such as cardiac beats, audio and ultrasonic range, calculating wavelet coefficients in real time, with processor clock running at frequency of present ASIC's and FPGA. The Paralell Filter Architecture for DWT has been improved, calculating wavelet coefficients in real time with hardware reduced to 60%. The new architecture, which also processes IDWT, is implemented with the Radix-2 or the Booth-Wallace Constant multipliers. Including series memory register banks, one integrated circuit Signal Analyzer, ultrasonic range, is presented.

Parametrized Architecture for Hough Transform Recursive Evaluation

Paper submitted to International Workshop on Spectral Methods and Multirate Signal Processing (SMMSP), Barcelona, España, 2003.

New fiber laser architecture with transform-limited nonlinear spectral compression

We numerically demonstrate a new fiber laser architecture supporting spectral compression of negatively chirped pulses in passive normally dispersive fiber. Such a process is beneficial for improving the energy efficiency of the cavity as it prevents narrow spectral filtering from being highly dissipative. The proposed laser design provides an elegant way of generating transform-limited picosecond pulses. © 2012 IEEE.

New fiber laser architecture with transform-limited nonlinear spectral compression

We numerically demonstrate a new fiber laser architecture supporting spectral compression of negatively chirped pulses in passive normally dispersive fiber. Such a process is beneficial for improving the energy efficiency of the cavity as it prevents narrow spectral filtering from being highly dissipative. The proposed laser design provides an elegant way of generating transform-limited picosecond pulses. © 2012 IEEE.

The myth of the nation: Historiography of New Zealand architecture since 1907

This paper considers the relationship between the recent historiography (of the last quarter century) of “New Zealand architecture” and the historical notion of “New Zealand-ness” invoked in contemporary architecture. It argues that a more recent programmatic uptake of post-War discussions on national identity and regional specificity has fed the tendencies of practicing architects to defer to history in rhetorical defences of their work: the beach-side mansion as a contemporary expression of the 1950s bach; a formal modernism divorced from the social discourse adherent to the historical moment that it “restates”; and so on. The paper will consider instances in the historiography of New Zealand architecture where historians have compounded, consciously or accidentally, a problem that is systemic to the uses made by architects of historical knowledge (in the most general examples), identifying the difficulties of relying upon the tentative conclusions of an under-studied field in developing principles of contemporary architectural practice under the banners of New Zealand-ness, regionalism, or localism, or with reference to icons of New Zealand architectural history. At the heart of this paper is a reflection on historiographical responsibility in presenting knowledge of a national past to an audience that is eager to transform that knowledge into principles of contemporary production. What, the paper asks, is the historical basis for speaking of a New Zealand architecture? Can we speak of a national history of architecture distinct from a regional history, or from an international history of architecture?

Statistical motion learning for improved transform domain Wyner-Ziv video coding

Wyner - Ziv (WZ) video coding is a particular case of distributed video coding (DVC), the recent video coding paradigm based on the Slepian - Wolf and Wyner - Ziv theorems which exploits the source temporal correlation at the decoder and not at the encoder as in predictive video coding. Although some progress has been made in the last years, WZ video coding is still far from the compression performance of predictive video coding, especially for high and complex motion contents. The WZ video codec adopted in this study is based on a transform domain WZ video coding architecture with feedback channel-driven rate control, whose modules have been improved with some recent coding tools. This study proposes a novel motion learning approach to successively improve the rate-distortion (RD) performance of the WZ video codec as the decoding proceeds, making use of the already decoded transform bands to improve the decoding process for the remaining transform bands. The results obtained reveal gains up to 2.3 dB in the RD curves against the performance for the same codec without the proposed motion learning approach for high motion sequences and long group of pictures (GOP) sizes.

A Flexible Architecture for the Computation of Direct and Inverse Transforms in H.264/AVC Video Codecs

A new high throughput and scalable architecture for unified transform coding in H.264/AVC is proposed in this paper. Such flexible structure is capable of computing all the 4x4 and 2x2 transforms for Ultra High Definition Video (UHDV) applications (4320x7680@ 30fps) in real-time and with low hardware cost. These significantly high performance levels were proven with the implementation of several different configurations of the proposed structure using both FPGA and ASIC 90 nm technologies. In addition, such experimental evaluation also demonstrated the high area efficiency of theproposed architecture, which in terms of Data Throughput per Unit of Area (DTUA) is at least 1.5 times more efficient than its more prominent related designs(1).

Mapping complex tissue architecture with diffusion spectrum magnetic resonance imaging.

Methods are presented to map complex fiber architectures in tissues by imaging the 3D spectra of tissue water diffusion with MR. First, theoretical considerations show why and under what conditions diffusion contrast is positive. Using this result, spin displacement spectra that are conventionally phase-encoded can be accurately reconstructed by a Fourier transform of the measured signal's modulus. Second, studies of in vitro and in vivo samples demonstrate correspondence between the orientational maxima of the diffusion spectrum and those of the fiber orientation density at each location. In specimens with complex muscular tissue, such as the tongue, diffusion spectrum images show characteristic local heterogeneities of fiber architectures, including angular dispersion and intersection. Cerebral diffusion spectra acquired in normal human subjects resolve known white matter tracts and tract intersections. Finally, the relation between the presented model-free imaging technique and other available diffusion MRI schemes is discussed.

A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection

This paper proposes a parallel hardware architecture for image feature detection based on the Scale Invariant Feature Transform algorithm and applied to the Simultaneous Localization And Mapping problem. The work also proposes specific hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect features up to 30 frames per second (320 x 240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several hardware-orientated optimizations oil performance, area and accuracy.

Molecular architecture of thin films fabricated via physical vapor deposition and containing a poly(azo)urethane

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Discrete wavelet transform signal analyzer

This paper addresses the problem of processing biological data, such as cardiac beats in the audio and ultrasonic range, and on calculating wavelet coefficients in real time, with the processor clock running at a frequency of present application-specified integrated circuits and field programmable gate array. The parallel filter architecture for discrete wavelet transform (DWT) has been improved, calculating the wavelet coefficients in real time with hardware reduced up to 60%. The new architecture, which also processes inverse DWT, is implemented with the Radix-2 or the Booth-Wallace constant multipliers. One integrated circuit signal analyzer in the ultrasonic range, including series memory register banks, is presented. © 2007 IEEE.

Digital signal processing and digital system design using discrete cosine transform [student course]

The discrete cosine transform (DCT) is an important functional block for image processing applications. The implementation of a DCT has been viewed as a specialized research task. We apply a micro-architecture based methodology to the hardware implementation of an efficient DCT algorithm in a digital design course. Several circuit optimization and design space exploration techniques at the register-transfer and logic levels are introduced in class for generating the final design. The students not only learn how the algorithm can be implemented, but also receive insights about how other signal processing algorithms can be translated into a hardware implementation. Since signal processing has very broad applications, the study and implementation of an extensively used signal processing algorithm in a digital design course significantly enhances the learning experience in both digital signal processing and digital design areas for the students.