A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection
Contribuinte(s) |
UNIVERSIDADE DE SÃO PAULO |
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Data(s) |
20/10/2012
20/10/2012
2008
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Resumo |
This paper proposes a parallel hardware architecture for image feature detection based on the Scale Invariant Feature Transform algorithm and applied to the Simultaneous Localization And Mapping problem. The work also proposes specific hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect features up to 30 frames per second (320 x 240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several hardware-orientated optimizations oil performance, area and accuracy. CAPES[BEX2683/06-7] Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) EPSRC EPSRC[EP/C549481/1] EPSRC EPSRC[EP/C512596/1] |
Identificador |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, v.18, n.12, p.1703-1712, 2008 1051-8215 http://producao.usp.br/handle/BDPI/28983 10.1109/TCSVT.2008.2004936 |
Idioma(s) |
eng |
Publicador |
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
Relação |
Ieee Transactions on Circuits and Systems for Video Technology |
Direitos |
restrictedAccess Copyright IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
Palavras-Chave | #Embedded robotics #field-programmable gate array (FPGA) #SIFT #SLAM #LOCALIZATION #Engineering, Electrical & Electronic |
Tipo |
article original article publishedVersion |