Case based reasoning as an extension of fault dictionary methods for linear electronic analog circuits diagnosis

El test de circuits és una fase del procés de producció que cada vegada pren més importància quan es desenvolupa un nou producte. Les tècniques de test i diagnosi per a circuits digitals han estat desenvolupades i automatitzades amb èxit, mentre que aquest no és encara el cas dels circuits analògics. D'entre tots els mètodes proposats per diagnosticar circuits analògics els més utilitzats són els diccionaris de falles. En aquesta tesi se'n descriuen alguns, tot analitzant-ne els seus avantatges i inconvenients. Durant aquests últims anys, les tècniques d'Intel·ligència Artificial han esdevingut un dels camps de recerca més importants per a la diagnosi de falles. Aquesta tesi desenvolupa dues d'aquestes tècniques per tal de cobrir algunes de les mancances que presenten els diccionaris de falles. La primera proposta es basa en construir un sistema fuzzy com a eina per identificar. Els resultats obtinguts son força bons, ja que s'aconsegueix localitzar la falla en un elevat tant percent dels casos. Per altra banda, el percentatge d'encerts no és prou bo quan a més a més s'intenta esbrinar la desviació. Com que els diccionaris de falles es poden veure com una aproximació simplificada al Raonament Basat en Casos (CBR), la segona proposta fa una extensió dels diccionaris de falles cap a un sistema CBR. El propòsit no és donar una solució general del problema sinó contribuir amb una nova metodologia. Aquesta consisteix en millorar la diagnosis dels diccionaris de falles mitjançant l'addició i l'adaptació dels nous casos per tal d'esdevenir un sistema de Raonament Basat en Casos. Es descriu l'estructura de la base de casos així com les tasques d'extracció, de reutilització, de revisió i de retenció, fent èmfasi al procés d'aprenentatge. En el transcurs del text s'utilitzen diversos circuits per mostrar exemples dels mètodes de test descrits, però en particular el filtre biquadràtic és l'utilitzat per provar les metodologies plantejades, ja que és un dels benchmarks proposats en el context dels circuits analògics. Les falles considerades son paramètriques, permanents, independents i simples, encara que la metodologia pot ser fàcilment extrapolable per a la diagnosi de falles múltiples i catastròfiques. El mètode es centra en el test dels components passius, encara que també es podria extendre per a falles en els actius.

Disseny d'un sistema HW/SW de control remot amb dispositius FPGA

El projecte que es presenta a continuació, té com a objectiu implementar un sistema HW/SW encastat en una FPGA, capaç d’executar funcions de control remot per infraroig en plataformes de televisió flexibles de Sony Corp. El disseny obtingut, s’incorporarà a un sistema més ampli de verificació i test de circuits impresos, dins del marc de producció SMD. La finalitat d’aquest projecte, és la realització d’un sistema flexible per a la implementació de comandaments de comunicació per infraroig amb circuits impresos. Prèviament, s’ha estudiat els conceptes bàsics referents a la implementació de sistemes amb FPGAs, la seva metodologia de desenvolupament i les principals característiques de la seva arquitectura. Com a especificacions, s’ha utilitzat l’estàndard de control remot per infraroig de Sony Corp SIRCS (Sony Infrared remote control system).

Ensayos acelerados de fiabilidad de células solares de concentración

SUMMARY Concentration Photovoltaic Systems (CPV) have been proposed as an alternative to conventional systems. During the last years, there has been a boom of the CPV industry caused by the technological progress in all the elements of the system. and mainly caused by the use of multijunction solar cells based on III-V semiconductors, with efficiencies exceeding to 43%. III-V solar cells have been used with high reliability results in a great number of space missions without concentration. However, there are no previous results regarding their reliability in concentration terrestrial applications, where the working conditions are completely different. This lack of experience, together with the important industrial interest, has generated the need to evaluate the reliability of the cells. For this reason, nowadays there are several research centers around the undertaking this task. The evaluation of the reliability of this type of devices by means of accelerated tests is especially problematic when they work at medium or high concentration, because it is practically impossible to emulate real working conditions of the cell inside climatic chambers. In fact, as far as we know, the results that appear in this Thesis are the first estimating the Activation Energy of the failure mechanism involved, as well as the warranty of the III-V concentrator solar cells tested here. To evaluate the reliability of III-V very high concentrator solar cells by means of accelerated tests, a variety of activities, described in this Thesis have been carried out. The First Part of the memory presents the theoretical part of the Doctoral Thesis. After the Introduction, chapter 2 presents the state of the art in degradation and reliability of CPV systems and solar cells. Chapter 3 introduces some reliability definitions and the application of specific statistical functions to the evaluation of the reliability and parameters. From these functions, important parameters will be calculated to be used later in the experimental results of Thesis. The Second Part of the memory contains the experimental. Chapter 4 shows the types of accelerated tests and the main goals pursuit with them when carried out over CPV systems and solar cells. In order to evaluate quantitatively the reliability of the III-V concentrator solar cells used in these tests, some modifications have been introduced which discussion will be tackled here. Based on this analysis the working plan of the tests carried out in this Doctoral Thesis is presented. Chapter 5 presents a new methodology as well as the necessary instrumentation to carry out the tests described here. This new methodology takes into account the adaptation, improvement and novel techniques needed to test concentrator solar cells. The core of this memory is chapter 6, which presents the results of the characterization of the cells during the accelerated life tests and the analysis of the aforementioned results with the purpose of getting quantitative values of reliability in real working conditions. The acceleration factor of the accelerated life tests, under nominal working conditions has been calculated. Accordingly, the validity of the methodology as well as the calculations based on the reliability assessment, have also been demonstrated. Finally, quantitative values of degradation, reliability and warranty of the solar cells under field nominal working conditions have been calculated. With the development of this Doctoral Thesis the reliability of very high concentrator GaAs solar cells of small area has been evaluated. It is very interesting to generalize the procedures described up to this point to III-V multijunction solar cells of greater area. Therefore, chapter 7 develops this generalization and introduces also a useful thermal modeling by means of finite elements of the test cells’ circuits. In the last chapter, the summary of the results and the main contributions of this Thesis are outlined and future research activities are identified. RESUMEN Los Sistemas Fotovoltaicos de Concentración (SFC) han sido propuestos como una alternativa a los sistemas convencionales de generación de energía. Durante los últimos años ha habido un auge de los SFC debido a las mejoras tecnológicas en todos los elementos del sistema, y principalmente por el uso de células multiunión III-V que superan el 43% de rendimiento. Las células solares III-V han sido utilizadas con elevada fiabilidad en aplicaciones espaciales sin concentración, pero no existe experiencia de su fiabilidad en ambiente terrestre a altos niveles de concentración solar. Esta falta de experiencia junto al gran interés industrial ha generado la necesidad de evaluar la fiabilidad de las células, y actualmente hay un significativo número de centros de investigación trabajando en esta área. La evaluación de la fiabilidad de este tipo de dispositivos mediante ensayos acelerados es especialmente problemática cuando trabajan a media o alta concentración por la casi imposibilidad de emular las condiciones de trabajo reales de la célula dentro de cámaras climáticas. De hecho, que sepamos, en los resultados de esta Tesis se evalúa por primera vez la Energía de Activación del mecanismo de fallo de las células, así como la garantía en campo de las células de concentración III-V analizadas. Para evaluar la fiabilidad de células solares III-V de muy alta concentración mediante ensayos de vida acelerada se han realizado diversas actividades que han sido descritas en la memoria de la Tesis. En la Primera Parte de la memoria se presenta la parte teórica de la Tesis Doctoral. Tras la Introducción, en el capítulo 2 se muestra el estado del arte en degradación y fiabilidad de células y Sistemas Fotovoltaicos de Concentración. En el capítulo 3 se exponen de forma resumida las definiciones de fiabilidad y funciones estadísticas que se utilizan para la evaluación de la fiabilidad y sus parámetros, las cuales se emplearán posteriormente en los ensayos descritos en este Tesis. La Segunda Parte de la memoria es experimental. En el capítulo 4 se describen los tipos y objetivos de los ensayos acelerados actualmente aplicados a SFC y a las células, así como las modificaciones necesarias que permitan evaluar cuantitativamente la fiabilidad de las células solares de concentración III-V. En base a este análisis se presenta la planificación de los trabajos realizados en esta Tesis Doctoral. A partir de esta planificación y debido a la necesidad de adaptar, mejorar e innovar las técnicas de ensayos de vida acelerada para una adecuada aplicación a este tipo de dispositivos, en el capítulo 5 se muestra la metodología empleada y la instrumentación necesaria para realizar los ensayos de esta Tesis Doctoral. El núcleo de la memoria es el capítulo 6, en él se presentan los resultados de caracterización de las células durante los ensayos de vida acelerada y el análisis de dichos resultados con el objetivo de obtener valores cuantitativos de fiabilidad en condiciones reales de trabajo. Se calcula el Factor de Aceleración de los ensayos acelerados con respecto a las condiciones nominales de funcionamiento a partir de la Energía de Activación obtenida, y se demuestra la validez de la metodología y cálculos empleados, que son la base de la evaluación de la fiabilidad. Finalmente se calculan valores cuantitativos de degradación, fiabilidad y garantía de las células en condiciones nominales en campo durante toda la vida de la célula. Con el desarrollo de esta Tesis Doctoral se ha evaluado la fiabilidad de células III-V de área pequeña, pero es muy interesante generalizar los procedimientos aquí desarrollados para las células III-V comerciales de área grande. Por este motivo, en el capítulo 7 se analiza dicha generalización, incluyendo el modelado térmico mediante elementos finitos de los circuitos de ensayo de las células. En el último capítulo se realiza un resume del trabajo y las aportaciones realizadas, y se identifican las líneas de trabajo a emprender en el futuro.

A test mode approach to fault detection in sequential circuits,

"C00-1469-0117."

ARPA/NBS workshop III : test patterns for integrated circuits /

Consists of synopses of talks and discussions presented at the workshop held Sept. 6, 1974 in Scottsdale, Ariz.

Fault current test of a bifilar Bi-2212 bulk coil

A bifilar Bi-2212 bulk coil with parallel shunt resistor was tested under fault current condition using a 3 MVA single-phase transformer in a 220 V-60 Hz line achieving fault current peak of 8 kA. The fault current tests are performed from steady state peak current of 200 A by applying controlled short circuits up to 8 kA varying the time period from one to six cycles. The test results show the function of the shunt resistor providing homogeneous quench behavior of the HTS coil besides its intrinsic stabilizing role. The limiting current ratio achieves a factor 4.2 during 5 cycles without any degradation.

Fuzzy risk index for power transformer failures due to external short-circuits

A novel methodology to assess the risk of power transformer failures caused by external faults, such as short-circuit, taking the paper insulation condition into account, is presented. The risk index is obtained by contrasting the insulation paper condition with the probability that the transformer withstands the short-circuit current flowing along the winding during an external fault. In order to assess the risk, this probability and the value of the degree of polymerization of the insulating paper are regarded as inputs of a type-2 fuzzy logic system (T2-FLS), which computes the fuzzy risk level. A Monte Carlo simulation has been used to find the survival function of the currents flowing through the transformer winding during a single-phase or a three-phase short-circuit. The Roy Billinton Test System and a real power system have been used to test the results. (C) 2008 Elsevier B.V. All rights reserved.

Selective involvement of GABAergic mechanisms of the dorsal periaqueductal gray and inferior colliculus on the memory of the contextual fear as assessed by the fear potentiated startle test

The inferior colliculus (IC) together with the dorsal periaqueductal gray (dPAG), the amygdala and the medial hypothalamus make part of the brain aversion system, which has mainly been related to the organization of unconditioned fear. However, the involvement of the IC and dPAG in the conditioned fear is still unclear. It is certain that GABA has a regulatory role on the aversive states generated and elaborated in these midbrain structures. In this study, we evaluated the effects of injections of the GABA-A receptor agonist muscimol (1.0 and 2.0 nmol/0.2 mu L) into the IC or dPAG on the freezing and fear-potentiated startle (FPS) responses of rats submitted to a context fear conditioning. Intra-IC injections of muscimol did not cause any significant effect on the FPS or conditioned freezing but enhanced the startle reflex in non-conditioned animals. In contrast, intra-dPAG injections of muscimol caused significant reduction in FPS and conditioned freezing without changing the startle reflex in non-conditioned animals. Thus, intra-dPAG injections of muscimol produced the expected inhibitory effects on the anxiety-related responses, the FPS and the freezing whereas these injections into the IC produced quite opposite effects suggesting that descending inhibitory pathways from the IC, probably mediated by GABA-A mechanisms, exert a regulatory role on the lower brainstem circuits responsible for the startle reflex. (C) 2008 Elsevier Inc. All rights reserved.

Water treatments in semi-closed cooling circuits and their impact on the quality of effluents discharged by CERN

Dissertação apresentada à Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia do Ambiente, Gestão de Sistemas Ambientais

Water treatments in semi-closed cooling circuits and their impact on the quality of effluents discharged by CERN

Mestrado integrado em Engenharia do Ambiente, perfil: Gestão de Sistemas Ambientais

From design-for-test to design-for-debug-and-test: analysis of requirements and limitations for 1149.1

The increasing complexity of VLSI circuits and the reduced accessibility of modern packaging and mounting technologies restrict the usefulness of conventional in-circuit debugging tools, such as in-circuit emulators for microprocessors and microcontrollers. However, this same trend enables the development of more complex products, which in turn require more powerful debugging tools. These conflicting demands could be met if the standard scan test infrastructures now common in most complex components were able to match the debugging requirements of design verification and prototype validation. This paper analyses the main debug requirements in the design of microprocessor-based applications and the feasibility of their implementation using the mandatory, optional and additional operating modes of the standard IEEE 1149.1 test infrastructure.

Emergence of oriented circuits driven by synaptic pruning associated with spike-timing-dependent plasticity (STDP)

ABSTRACT: Massive synaptic pruning following over-growth is a general feature of mammalian brain maturation. Pruning starts near time of birth and is completed by time of sexual maturation. Trigger signals able to induce synaptic pruning could be related to dynamic functions that depend on the timing of action potentials. Spike-timing-dependent synaptic plasticity (STDP) is a change in the synaptic strength based on the ordering of pre- and postsynaptic spikes. The relation between synaptic efficacy and synaptic pruning suggests that the weak synapses may be modified and removed through competitive "learning" rules. This plasticity rule might produce the strengthening of the connections among neurons that belong to cell assemblies characterized by recurrent patterns of firing. Conversely, the connections that are not recurrently activated might decrease in efficiency and eventually be eliminated. The main goal of our study is to determine whether or not, and under which conditions, such cell assemblies may emerge out of a locally connected random network of integrate-and-fire units distributed on a 2D lattice receiving background noise and content-related input organized in both temporal and spatial dimensions. The originality of our study stands on the relatively large size of the network, 10,000 units, the duration of the experiment, 10E6 time units (one time unit corresponding to the duration of a spike), and the application of an original bio-inspired STDP modification rule compatible with hardware implementation. A first batch of experiments was performed to test that the randomly generated connectivity and the STDP-driven pruning did not show any spurious bias in absence of stimulation. Among other things, a scale factor was approximated to compensate for the network size on the ac¬tivity. Networks were then stimulated with the spatiotemporal patterns. The analysis of the connections remaining at the end of the simulations, as well as the analysis of the time series resulting from the interconnected units activity, suggest that feed-forward circuits emerge from the initially randomly connected networks by pruning. RESUME: L'élagage massif des synapses après une croissance excessive est une phase normale de la ma¬turation du cerveau des mammifères. L'élagage commence peu avant la naissance et est complété avant l'âge de la maturité sexuelle. Les facteurs déclenchants capables d'induire l'élagage des synapses pourraient être liés à des processus dynamiques qui dépendent de la temporalité rela¬tive des potentiels d'actions. La plasticité synaptique à modulation temporelle relative (STDP) correspond à un changement de la force synaptique basé sur l'ordre des décharges pré- et post- synaptiques. La relation entre l'efficacité synaptique et l'élagage des synapses suggère que les synapses les plus faibles pourraient être modifiées et retirées au moyen d'une règle "d'appren¬tissage" faisant intervenir une compétition. Cette règle de plasticité pourrait produire le ren¬forcement des connexions parmi les neurones qui appartiennent à une assemblée de cellules caractérisée par des motifs de décharge récurrents. A l'inverse, les connexions qui ne sont pas activées de façon récurrente pourraient voir leur efficacité diminuée et être finalement éliminées. Le but principal de notre travail est de déterminer s'il serait possible, et dans quelles conditions, que de telles assemblées de cellules émergent d'un réseau d'unités integrate-and¬-fire connectées aléatoirement et distribuées à la surface d'une grille bidimensionnelle recevant à la fois du bruit et des entrées organisées dans les dimensions temporelle et spatiale. L'originalité de notre étude tient dans la taille relativement grande du réseau, 10'000 unités, dans la durée des simulations, 1 million d'unités de temps (une unité de temps correspondant à une milliseconde), et dans l'utilisation d'une règle STDP originale compatible avec une implémentation matérielle. Une première série d'expériences a été effectuée pour tester que la connectivité produite aléatoirement et que l'élagage dirigé par STDP ne produisaient pas de biais en absence de stimu¬lation extérieure. Entre autres choses, un facteur d'échelle a pu être approximé pour compenser l'effet de la variation de la taille du réseau sur son activité. Les réseaux ont ensuite été stimulés avec des motifs spatiotemporels. L'analyse des connexions se maintenant à la fin des simulations, ainsi que l'analyse des séries temporelles résultantes de l'activité des neurones, suggèrent que des circuits feed-forward émergent par l'élagage des réseaux initialement connectés au hasard.

Preliminary Characterisation of Low-Temperature Bonded Copper Interconnects for 3-D Integrated Circuits

Three dimensional (3-D) integrated circuits can be fabricated by bonding previously processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnects test structures were created by thermocompression bonding and the bond toughness was measured using the four-point test. The effects of bonding temperature, physical bonding and failure mechanisms were investigated. The surface effects on copper surface due to pre-bond clean (with glacial acetic acid) were also looked into. A maximum average bond toughness of approximately 35 J/m² was obtained bonding temperature 300 C.

Functional timing analysis of VLSI circuits containing complex gates

The recent advances in CMOS technology have allowed for the fabrication of transistors with submicronic dimensions, making possible the integration of tens of millions devices in a single chip that can be used to build very complex electronic systems. Such increase in complexity of designs has originated a need for more efficient verification tools that could incorporate more appropriate physical and computational models. Timing verification targets at determining whether the timing constraints imposed to the design may be satisfied or not. It can be performed by using circuit simulation or by timing analysis. Although simulation tends to furnish the most accurate estimates, it presents the drawback of being stimuli dependent. Hence, in order to ensure that the critical situation is taken into account, one must exercise all possible input patterns. Obviously, this is not possible to accomplish due to the high complexity of current designs. To circumvent this problem, designers must rely on timing analysis. Timing analysis is an input-independent verification approach that models each combinational block of a circuit as a direct acyclic graph, which is used to estimate the critical delay. First timing analysis tools used only the circuit topology information to estimate circuit delay, thus being referred to as topological timing analyzers. However, such method may result in too pessimistic delay estimates, since the longest paths in the graph may not be able to propagate a transition, that is, may be false. Functional timing analysis, in turn, considers not only circuit topology, but also the temporal and functional relations between circuit elements. Functional timing analysis tools may differ by three aspects: the set of sensitization conditions necessary to declare a path as sensitizable (i.e., the so-called path sensitization criterion), the number of paths simultaneously handled and the method used to determine whether sensitization conditions are satisfiable or not. Currently, the two most efficient approaches test the sensitizability of entire sets of paths at a time: one is based on automatic test pattern generation (ATPG) techniques and the other translates the timing analysis problem into a satisfiability (SAT) problem. Although timing analysis has been exhaustively studied in the last fifteen years, some specific topics have not received the required attention yet. One such topic is the applicability of functional timing analysis to circuits containing complex gates. This is the basic concern of this thesis. In addition, and as a necessary step to settle the scenario, a detailed and systematic study on functional timing analysis is also presented.

Mixed-signal analog-digital circuits design on the pre-diffused digital array using trapezoidal association of transistors

The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side, block components (Comparator and Folded-cascode OTA) of the Sigma-Delta modulator.