Case based reasoning as an extension of fault dictionary methods for linear electronic analog circuits diagnosis

El test de circuits és una fase del procés de producció que cada vegada pren més importància quan es desenvolupa un nou producte. Les tècniques de test i diagnosi per a circuits digitals han estat desenvolupades i automatitzades amb èxit, mentre que aquest no és encara el cas dels circuits analògics. D'entre tots els mètodes proposats per diagnosticar circuits analògics els més utilitzats són els diccionaris de falles. En aquesta tesi se'n descriuen alguns, tot analitzant-ne els seus avantatges i inconvenients. Durant aquests últims anys, les tècniques d'Intel·ligència Artificial han esdevingut un dels camps de recerca més importants per a la diagnosi de falles. Aquesta tesi desenvolupa dues d'aquestes tècniques per tal de cobrir algunes de les mancances que presenten els diccionaris de falles. La primera proposta es basa en construir un sistema fuzzy com a eina per identificar. Els resultats obtinguts son força bons, ja que s'aconsegueix localitzar la falla en un elevat tant percent dels casos. Per altra banda, el percentatge d'encerts no és prou bo quan a més a més s'intenta esbrinar la desviació. Com que els diccionaris de falles es poden veure com una aproximació simplificada al Raonament Basat en Casos (CBR), la segona proposta fa una extensió dels diccionaris de falles cap a un sistema CBR. El propòsit no és donar una solució general del problema sinó contribuir amb una nova metodologia. Aquesta consisteix en millorar la diagnosis dels diccionaris de falles mitjançant l'addició i l'adaptació dels nous casos per tal d'esdevenir un sistema de Raonament Basat en Casos. Es descriu l'estructura de la base de casos així com les tasques d'extracció, de reutilització, de revisió i de retenció, fent èmfasi al procés d'aprenentatge. En el transcurs del text s'utilitzen diversos circuits per mostrar exemples dels mètodes de test descrits, però en particular el filtre biquadràtic és l'utilitzat per provar les metodologies plantejades, ja que és un dels benchmarks proposats en el context dels circuits analògics. Les falles considerades son paramètriques, permanents, independents i simples, encara que la metodologia pot ser fàcilment extrapolable per a la diagnosi de falles múltiples i catastròfiques. El mètode es centra en el test dels components passius, encara que també es podria extendre per a falles en els actius.

Ensayos acelerados de fiabilidad de células solares de concentración

SUMMARY Concentration Photovoltaic Systems (CPV) have been proposed as an alternative to conventional systems. During the last years, there has been a boom of the CPV industry caused by the technological progress in all the elements of the system. and mainly caused by the use of multijunction solar cells based on III-V semiconductors, with efficiencies exceeding to 43%. III-V solar cells have been used with high reliability results in a great number of space missions without concentration. However, there are no previous results regarding their reliability in concentration terrestrial applications, where the working conditions are completely different. This lack of experience, together with the important industrial interest, has generated the need to evaluate the reliability of the cells. For this reason, nowadays there are several research centers around the undertaking this task. The evaluation of the reliability of this type of devices by means of accelerated tests is especially problematic when they work at medium or high concentration, because it is practically impossible to emulate real working conditions of the cell inside climatic chambers. In fact, as far as we know, the results that appear in this Thesis are the first estimating the Activation Energy of the failure mechanism involved, as well as the warranty of the III-V concentrator solar cells tested here. To evaluate the reliability of III-V very high concentrator solar cells by means of accelerated tests, a variety of activities, described in this Thesis have been carried out. The First Part of the memory presents the theoretical part of the Doctoral Thesis. After the Introduction, chapter 2 presents the state of the art in degradation and reliability of CPV systems and solar cells. Chapter 3 introduces some reliability definitions and the application of specific statistical functions to the evaluation of the reliability and parameters. From these functions, important parameters will be calculated to be used later in the experimental results of Thesis. The Second Part of the memory contains the experimental. Chapter 4 shows the types of accelerated tests and the main goals pursuit with them when carried out over CPV systems and solar cells. In order to evaluate quantitatively the reliability of the III-V concentrator solar cells used in these tests, some modifications have been introduced which discussion will be tackled here. Based on this analysis the working plan of the tests carried out in this Doctoral Thesis is presented. Chapter 5 presents a new methodology as well as the necessary instrumentation to carry out the tests described here. This new methodology takes into account the adaptation, improvement and novel techniques needed to test concentrator solar cells. The core of this memory is chapter 6, which presents the results of the characterization of the cells during the accelerated life tests and the analysis of the aforementioned results with the purpose of getting quantitative values of reliability in real working conditions. The acceleration factor of the accelerated life tests, under nominal working conditions has been calculated. Accordingly, the validity of the methodology as well as the calculations based on the reliability assessment, have also been demonstrated. Finally, quantitative values of degradation, reliability and warranty of the solar cells under field nominal working conditions have been calculated. With the development of this Doctoral Thesis the reliability of very high concentrator GaAs solar cells of small area has been evaluated. It is very interesting to generalize the procedures described up to this point to III-V multijunction solar cells of greater area. Therefore, chapter 7 develops this generalization and introduces also a useful thermal modeling by means of finite elements of the test cells’ circuits. In the last chapter, the summary of the results and the main contributions of this Thesis are outlined and future research activities are identified. RESUMEN Los Sistemas Fotovoltaicos de Concentración (SFC) han sido propuestos como una alternativa a los sistemas convencionales de generación de energía. Durante los últimos años ha habido un auge de los SFC debido a las mejoras tecnológicas en todos los elementos del sistema, y principalmente por el uso de células multiunión III-V que superan el 43% de rendimiento. Las células solares III-V han sido utilizadas con elevada fiabilidad en aplicaciones espaciales sin concentración, pero no existe experiencia de su fiabilidad en ambiente terrestre a altos niveles de concentración solar. Esta falta de experiencia junto al gran interés industrial ha generado la necesidad de evaluar la fiabilidad de las células, y actualmente hay un significativo número de centros de investigación trabajando en esta área. La evaluación de la fiabilidad de este tipo de dispositivos mediante ensayos acelerados es especialmente problemática cuando trabajan a media o alta concentración por la casi imposibilidad de emular las condiciones de trabajo reales de la célula dentro de cámaras climáticas. De hecho, que sepamos, en los resultados de esta Tesis se evalúa por primera vez la Energía de Activación del mecanismo de fallo de las células, así como la garantía en campo de las células de concentración III-V analizadas. Para evaluar la fiabilidad de células solares III-V de muy alta concentración mediante ensayos de vida acelerada se han realizado diversas actividades que han sido descritas en la memoria de la Tesis. En la Primera Parte de la memoria se presenta la parte teórica de la Tesis Doctoral. Tras la Introducción, en el capítulo 2 se muestra el estado del arte en degradación y fiabilidad de células y Sistemas Fotovoltaicos de Concentración. En el capítulo 3 se exponen de forma resumida las definiciones de fiabilidad y funciones estadísticas que se utilizan para la evaluación de la fiabilidad y sus parámetros, las cuales se emplearán posteriormente en los ensayos descritos en este Tesis. La Segunda Parte de la memoria es experimental. En el capítulo 4 se describen los tipos y objetivos de los ensayos acelerados actualmente aplicados a SFC y a las células, así como las modificaciones necesarias que permitan evaluar cuantitativamente la fiabilidad de las células solares de concentración III-V. En base a este análisis se presenta la planificación de los trabajos realizados en esta Tesis Doctoral. A partir de esta planificación y debido a la necesidad de adaptar, mejorar e innovar las técnicas de ensayos de vida acelerada para una adecuada aplicación a este tipo de dispositivos, en el capítulo 5 se muestra la metodología empleada y la instrumentación necesaria para realizar los ensayos de esta Tesis Doctoral. El núcleo de la memoria es el capítulo 6, en él se presentan los resultados de caracterización de las células durante los ensayos de vida acelerada y el análisis de dichos resultados con el objetivo de obtener valores cuantitativos de fiabilidad en condiciones reales de trabajo. Se calcula el Factor de Aceleración de los ensayos acelerados con respecto a las condiciones nominales de funcionamiento a partir de la Energía de Activación obtenida, y se demuestra la validez de la metodología y cálculos empleados, que son la base de la evaluación de la fiabilidad. Finalmente se calculan valores cuantitativos de degradación, fiabilidad y garantía de las células en condiciones nominales en campo durante toda la vida de la célula. Con el desarrollo de esta Tesis Doctoral se ha evaluado la fiabilidad de células III-V de área pequeña, pero es muy interesante generalizar los procedimientos aquí desarrollados para las células III-V comerciales de área grande. Por este motivo, en el capítulo 7 se analiza dicha generalización, incluyendo el modelado térmico mediante elementos finitos de los circuitos de ensayo de las células. En el último capítulo se realiza un resume del trabajo y las aportaciones realizadas, y se identifican las líneas de trabajo a emprender en el futuro.

V-Transform: “An Enhanced Polynomial Coefficient Based DC Test for Non-linear Analog Circuits

Abstract—DC testing of parametric faults in non-linear analog circuits based on a new transformation, entitled, V-Transform acting on polynomial coefficient expansion of the circuit function is presented. V-Transform serves the dual purpose of monotonizing polynomial coefficients of circuit function expansion and increasing the sensitivity of these coefficients to circuit parameters. The sensitivity of V-Transform Coefficients (VTC) to circuit parameters is up to 3x-5x more than sensitivity of polynomial coefficients. As a case study, we consider a benchmark elliptic filter to validate our method. The technique is shown to uncover hitherto untestable parametric faults whose sizes are smaller than 10 % of the nominal values. I.

Test-pattern selection for screening small-delay defects in very-deep submicrometer integrated circuits

Timing-related defects are major contributors to test escapes and in-field reliability problems for very-deep submicrometer integrated circuits. Small delay variations induced by crosstalk, process variations, power-supply noise, as well as resistive opens and shorts can potentially cause timing failures in a design, thereby leading to quality and reliability concerns. We present a test-grading technique that uses the method of output deviations for screening small-delay defects (SDDs). A new gate-delay defect probability measure is defined to model delay variations for nanometer technologies. The proposed technique intelligently selects the best set of patterns for SDD detection from an n-detect pattern set generated using timing-unaware automatic test-pattern generation (ATPG). It offers significantly lower computational complexity and excites a larger number of long paths compared to a current generation commercial timing-aware ATPG tool. Our results also show that, for the same pattern count, the selected patterns provide more effective coverage ramp-up than timing-aware ATPG and a recent pattern-selection method for random SDDs potentially caused by resistive shorts, resistive opens, and process variations. © 2010 IEEE.

A test mode approach to fault detection in sequential circuits,

"C00-1469-0117."

ARPA/NBS workshop III : test patterns for integrated circuits /

Consists of synopses of talks and discussions presented at the workshop held Sept. 6, 1974 in Scottsdale, Ariz.

Multi-Tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients

A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies in addition to DC. Classification or Cur is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. This testing method requires no design for test hardware as might be added to the circuit fly some other methods. The proposed method is illustrated for a benchmark elliptic filter. It is shown to uncover several parametric faults causing deviations as small as 5% from the nominal values.

On Minimization of Test Application Time for RAS

Conventional Random access scan (RAS) for testing has lower test application time, low power dissipation, and low test data volume compared to standard serial scan chain based design In this paper, we present two cluster based techniques, namely, Serial Input Random Access Scan and Variable Word Length Random Access Scan to reduce test application time even further by exploiting the parallelism among the clusters and performing write operations on multiple bits Experimental results on benchmarks circuits show on an average 2-3 times speed up in test write time and average 60% reduction in write test data volume

Test Application Time Minimization for RAS using Basis Optimization of Column Decoder

Random Access Scan, which addresses individual flip-flops in a design using a memory array like row and column decoder architecture, has recently attracted widespread attention, due to its potential for lower test application time, test data volume and test power dissipation when compared to traditional Serial Scan. This is because typically only a very limited number of random ``care'' bits in a test response need be modified to create the next test vector. Unlike traditional scan, most flip-flops need not be updated. Test application efficiency can be further improved by organizing the access by word instead of by bit. In this paper we present a new decoder structure that takes advantage of basis vectors and linear algebra to further significantly optimize test application in RAS by performing the write operations on multiple bits consecutively. Simulations performed on benchmark circuits show an average of 2-3 times speed up in test write time compared to conventional RAS.

In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits

An in-situ power monitoring technique for Dynamic Voltage and Threshold scaling (DVTS) systems is proposed which measures total power consumed by load circuit using sleep transistor acting as power sensor. Design details of power monitor are examined using simulation framework in UMC 90nm CMOS process. Experimental results of test chip fabricated in AMS 0.35µm CMOS process are presented. The test chip has variable activity between 0.05 and 0.5 and has PMOS VTH control through nWell contact. Maximum resolution obtained from power monitor is 0.25mV. Overhead of power monitor in terms of its power consumption is 0.244 mW (2.2% of total power of load circuit). Lastly, power monitor is used to demonstrate closed loop DVTS system. DVTS algorithm shows 46.3% power savings using in-situ power monitor.

Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits

Abstract—A method of testing for parametric faults of analog circuits based on a polynomial representaion of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies apart from DC. Classification of CUT is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. The method needs very little augmentation of circuit to make it testable as only output parameters are used for classification. This procedure is shown to uncover several parametric faults causing smaller than 5 % deviations the nominal values. Fault diagnosis based upon sensitivity of polynomial coefficients at relevant frequencies is also proposed.

Analog/RF Built-in-Self-Test Subsystem for a Mobile Broadcast Video Receiver in 65-nm CMOS

A built-in-self-test (BIST) subsystem embedded in a 65-nm mobile broadcast video receiver is described. The subsystem is designed to perform analog and RF measurements at multiple internal nodes of the receiver. It uses a distributed network of CMOS sensors and a low bandwidth, 12-bit A/D converter to perform the measurements with a serial bus interface enabling a digital transfer of measured data to automatic test equipment (ATE). A perturbation/correlation based BIST method is described, which makes pass/fail determination on parts, resulting in significant test time and cost reduction.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test

A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an analog voltage. This analog voltage controls the delay between this pair of clock signals, which is then measured in an all-digital manner using the technique of sub-sampling. This sub-sampling technique, having measurement time and accuracy trade-off, is well suited for low bandwidth signals. This concept is validated by designing delay cells, using current starved inverters in UMC 130nm CMOS process. Sub-mV accuracy is demonstrated for a measurement time of few seconds.