Double star chopper cell converter for battery electric vehicles with inter-module SoC balancing and fault tolerant control

A modularized battery system with Double Star Chopper Cell (DSCC) based modular multilevel converter is proposed for a battery operated electric vehicle (EV). A design concept for the modularized battery micro-packs for DSCC is described. Multidimensional pulse width modulation (MD-PWM) with integrated inter-module SoC balancing and fault tolerant control is proposed and explained. The DSCC can be operated either as an inverter to drive the EV motor or as a synchronous rectifier connected to external three phase power supply equipment for charging the battery micro-packs. The methods of operation as inverter and synchronous rectifier with integrated inter-module SoC balancing and fault tolerant control are discussed. The proposed system operation as inverter and synchronous rectifier are verified through simulations and the results are presented.

RETHROTTLE: Execution Throttling in the REDEFINE SoC Architecture

REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation (to expose abundant parallelism in applications) and runtime composition of efficient compute structures (on the reconfigurable computation resources). We propose and study the throttling of execution in REDEFINE to maximize the architecture efficiency. A feature specific fast hybrid (mixed level) simulation framework for early in design phase study is developed and implemented to make the huge design space exploration practical. We do performance modeling in terms of selection of important performance criteria, ranking of the explored throttling schemes and investigate effectiveness of the design space exploration using statistical hypothesis testing. We find throttling schemes which give appreciable (24.8%) overall performance gain in the architecture and 37% resource usage gain in the throttling unit simultaneously.

A Systematic Approach to Synthesis of Verification Test-suites for Modular SoC Designs

Verification is one of the important stages in designing an SoC (system on chips) that consumes upto 70% of the design time. In this work, we present a methodology to automatically generate verification test-cases to verify a class of SoCs and also enable re-use of verification resources created from one SoC to another. A prototype implementation for generating the test-cases is also presented.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures

In this paper we propose the architecture of a SoC fabric onto which applications described in a HLL are synthesized. The fabric is a homogeneous layout of computation, storage and communication resources on silicon. Through a process of composition of resources (as opposed to decomposition of applications), application specific computational structures are defined on the fabric at runtime to realize different modules of the applications in hardware. Applications synthesized on this fabric offers performance comparable to ASICs while retaining the programmability of processing cores. We outline the application synthesis methodology through examples, and compare our results with software implementations on traditional platforms with unbounded resources.

“Post silicon debug of SOC designs”

Continuous advances in VLSI technology have made implementation of very complicated systems possible. Modern System-on -Chips (SoCs) have many processors, IP cores and other functional units. As a result, complete verification of whole systems before implementation is becoming infeasible; hence it is likely that these systems may have some errors after manufacturing. This increases the need to find design errors in chips after fabrication. The main challenge for post-silicon debug is the observability of the internal signals. Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall verification effort on large designs, and the problem is growing worse.Traditional post-silicon debug methods concentrate on functional parts of systems and provide mechanisms to increase the observability of internal state of systems. Those methods may not be sufficient as modern SoCs have lots of blocks (processors, IP cores, etc.) which are communicating with one another and communication is another source of design errors. This tutorial will be provide an insight into various observability enhancement techniques, on chip instrumentation techniques and use of high level models to support the debug process targeting both inside blocks and communication among them. It will also cover the use of formal methods to help debug process.

System-level SoC near-field (NF) emissions: Simulation to measurement correlation

As System-on-Chip (SoC) designs migrate to 28nm process node and beyond, the electromagnetic (EM) co-interactions of the Chip-Package-Printed Circuit Board (PCB) becomes critical and require accurate and efficient characterization and verification. In this paper a fast, scalable, and parallelized boundary element based integral EM solutions to Maxwell equations is presented. The accuracy of the full-wave formulation, for complete EM characterization, has been validated on both canonical structures and real-world 3-D system (viz. Chip + Package + PCB). Good correlation between numerical simulation and measurement has been achieved. A few examples of the applicability of the formulation to high speed digital and analog serial interfaces on a 45nm SoC are also presented.

The presence in the Marche of Sericostoma siculum McL. (Insecta-Trichoptera). Translation from: Boll.Soc.eustachiana 43(2), 47-50, 1950]

The caddisfly (Trichoptera) Sericostoma siculum was found in the Marche region in Italy. The article summarises biology and ecology of the caddisfly, focusing on the larvae stage.

Experimental culture of algal balls (Cladophora sauteri). Retention of original shape [Translation from: Bull.Jap.Soc.Phycol. Vol. 10, (1), p. 23-27, 1962]

It was on July 1960 when 10 algal balls were acquired for exhibition at Suma Aquarium, Kobe. Permission to remove the specimens from the Lake Akan Reserve was given by the National Nature Reserve Committee. Algal balls, as a rule, lose their natural beauty when they are kept in an ordinary tank for a certain length of time. In an effort to retain the natural beauty it was decided to exhibit them in culture. This paper summarises the findings of this experiments with Cladophora sauteri. The author concludes that serious consideration has to be given as to the intensity of light, the sunlight, the water temperature and the nutrition for algal balls in culture in order to retain the natural beauty and shape.

The content of organic matter in some waters in the Moscow region [Translation from: C.R. Acad. Soc. URSS, 61, 293-296, 1948]

There is at the moment no direct method of determining the organic matter content of natural waters. In 1940/41 8 different water bodies in central Russia were studied and their organic matter identified. The author concludes that there is currently no easy method to determine organic matter in water. A number methods need to be applied.