Read-only-memory-based quantum computation: Experimental explorations using nuclear magnetic resonance and future prospects

Read-only-memory-based (ROM-based) quantum computation (QC) is an alternative to oracle-based QC. It has the advantages of being less magical, and being more suited to implementing space-efficient computation (i.e., computation using the minimum number of writable qubits). Here we consider a number of small (one- and two-qubit) quantum algorithms illustrating different aspects of ROM-based QC. They are: (a) a one-qubit algorithm to solve the Deutsch problem; (b) a one-qubit binary multiplication algorithm; (c) a two-qubit controlled binary multiplication algorithm; and (d) a two-qubit ROM-based version of the Deutsch-Jozsa algorithm. For each algorithm we present experimental verification using nuclear magnetic resonance ensemble QC. The average fidelities for the implementation were in the ranges 0.9-0.97 for the one-qubit algorithms, and 0.84-0.94 for the two-qubit algorithms. We conclude with a discussion of future prospects for ROM-based quantum computation. We propose a four-qubit algorithm, using Grover's iterate, for solving a miniature real-world problem relating to the lengths of paths in a network.

Minimum mean running time function generation using read only memory /

Vita.

Write-erase and read paper memory transistor

Applied Physics Letters, Vol.93, issue 20

Analytic model of a cache-only memory architecture

An approximate analytic model of a shared memory multiprocessor with a Cache Only Memory Architecture (COMA), the busbased Data Difussion Machine (DDM), is presented and validated. It describes the timing and interference in the system as a function of the hardware, the protocols, the topology and the workload. Model results have been compared to results from an independent simulator. The comparison shows good model accuracy specially for non-saturated systems, where the errors in response times and device utilizations are independent of the number of processors and remain below 10% in 90% of the simulations. Therefore, the model can be used as an average performance prediction tool that avoids expensive simulations in the design of systems with many processors.

ROM-based computation: Quantum versus classical

We introduce a model of computation based on read only memory (ROM), which allows us to compare the space-efficiency of reversible, error-free classical computation with reversible, error-free quantum computation. We show that a ROM-based quantum computer with one writable qubit is universal, whilst two writable bits are required for a universal classical ROM-based computer. We also comment on the time-efficiency advantages of quantum computation within this model.

Implementação de um protótipo de uma aplicação multimídia sobre a Ilha Rei George, Antártica

Esta dissertação aborda a implementação de um protótipo de aplicação multimídia referente à Ilha Rei George (61º 50’ S, 57º 30’ W e 62º 15’ S, 59º 00' W), Antártica. Nessa ilha o Brasil mantém sua única estação polar, onde realiza parte das pesquisas do Programa Antártico Brasileiro (PROANTAR). O presente trabalho visa reduzir a carência por materiais didáticos em língua portuguesa sobre as regiões polares e aborda aspectos gerais da biota, geografia física (geologia, climatologia e oceanografia) e geografia humana (história de ocupação, turismo, pesquisa e impactos gerados pela presença humana). O público alvo são pessoas com nível de instrução de ensino médio incompleto ou níveis mais avançados. O conteúdo é apresentado de forma a cativar a atenção do usuário, sem exageros estéticos. A fim de obter material para subsidiar o projeto, foram realizados registros por meio de fotografias, gravações em vídeo e entrevistas durante os trabalhos de campo na ilha, realizados no verão de 2004. Além dos registros em campo, são apresentados materiais didáticos tais como textos, ilustrações e animações em 3D. Parte do material gerado está disponível para utilização posterior em outros projetos O ambiente de desenvolvimento utilizado para a aplicação foi o Macromedia Director, para Apple Macintosh. O produto do projeto é um protótipo que pode ser distribuído em mídia removível, CD-ROM (Compact Disk Read Only Memory) ou DVD-ROM (Digital Versatile Disc Read Only Memory) e é encontrado como um encarte no final desta dissertação. A informação compilada e reunida na aplicação permite ao público acesso a dados atualizados sobre o ambiente antártico de forma simples, didática e interativa. O trabalho esclarece as relações entre a Antártica e o mundo, principalmente no que faz referência à ilha Rei George, buscando a valorização das regiões polares.

Práticas de formação continuada da EJA pelo olhar investigativo da formadora

Pós-graduação em Educação - IBRC

Software transactional memory as a building block for parallel embedded realtime systems

The recent trends of chip architectures with higher number of heterogeneous cores, and non-uniform memory/non-coherent caches, brings renewed attention to the use of Software Transactional Memory (STM) as a fundamental building block for developing parallel applications. Nevertheless, although STM promises to ease concurrent and parallel software development, it relies on the possibility of aborting conflicting transactions to maintain data consistency, which impacts on the responsiveness and timing guarantees required by embedded real-time systems. In these systems, contention delays must be (efficiently) limited so that the response times of tasks executing transactions are upper-bounded and task sets can be feasibly scheduled. In this paper we assess the use of STM in the development of embedded real-time software, defending that the amount of contention can be reduced if read-only transactions access recent consistent data snapshots, progressing in a wait-free manner. We show how the required number of versions of a shared object can be calculated for a set of tasks. We also outline an algorithm to manage conflicts between update transactions that prevents starvation.

Scaling In-Memory databases on multicores

Current computer systems have evolved from featuring only a single processing unit and limited RAM, in the order of kilobytes or few megabytes, to include several multicore processors, o↵ering in the order of several tens of concurrent execution contexts, and have main memory in the order of several tens to hundreds of gigabytes. This allows to keep all data of many applications in the main memory, leading to the development of inmemory databases. Compared to disk-backed databases, in-memory databases (IMDBs) are expected to provide better performance by incurring in less I/O overhead. In this dissertation, we present a scalability study of two general purpose IMDBs on multicore systems. The results show that current general purpose IMDBs do not scale on multicores, due to contention among threads running concurrent transactions. In this work, we explore di↵erent direction to overcome the scalability issues of IMDBs in multicores, while enforcing strong isolation semantics. First, we present a solution that requires no modification to either database systems or to the applications, called MacroDB. MacroDB replicates the database among several engines, using a master-slave replication scheme, where update transactions execute on the master, while read-only transactions execute on slaves. This reduces contention, allowing MacroDB to o↵er scalable performance under read-only workloads, while updateintensive workloads su↵er from performance loss, when compared to the standalone engine. Second, we delve into the database engine and identify the concurrency control mechanism used by the storage sub-component as a scalability bottleneck. We then propose a new locking scheme that allows the removal of such mechanisms from the storage sub-component. This modification o↵ers performance improvement under all workloads, when compared to the standalone engine, while scalability is limited to read-only workloads. Next we addressed the scalability limitations for update-intensive workloads, and propose the reduction of locking granularity from the table level to the attribute level. This further improved performance for intensive and moderate update workloads, at a slight cost for read-only workloads. Scalability is limited to intensive-read and read-only workloads. Finally, we investigate the impact applications have on the performance of database systems, by studying how operation order inside transactions influences the database performance. We then propose a Read before Write (RbW) interaction pattern, under which transaction perform all read operations before executing write operations. The RbW pattern allowed TPC-C to achieve scalable performance on our modified engine for all workloads. Additionally, the RbW pattern allowed our modified engine to achieve scalable performance on multicores, almost up to the total number of cores, while enforcing strong isolation.

Improvements in Hardware Transactional Memory for GPU Architectures

In the multi-core CPU world, transactional memory (TM)has emerged as an alternative to lock-based programming for thread synchronization. Recent research proposes the use of TM in GPU architectures, where a high number of computing threads, organized in SIMT fashion, requires an effective synchronization method. In contrast to CPUs, GPUs offer two memory spaces: global memory and local memory. The local memory space serves as a shared scratch-pad for a subset of the computing threads, and it is used by programmers to speed-up their applications thanks to its low latency. Prior work from the authors proposed a lightweight hardware TM (HTM) support based in the local memory, modifying the SIMT execution model and adding a conflict detection mechanism. An efficient implementation of these features is key in order to provide an effective synchronization mechanism at the local memory level. After a quick description of the main features of our HTM design for GPU local memory, in this work we gather together a number of proposals designed with the aim of improving those mechanisms with high impact on performance. Firstly, the SIMT execution model is modified to increase the parallelism of the application when transactions must be serialized in order to make forward progress. Secondly, the conflict detection mechanism is optimized depending on application characteristics, such us the read/write sets, the probability of conflict between transactions and the existence of read-only transactions. As these features can be present in hardware simultaneously, it is a task of the compiler and runtime to determine which ones are more important for a given application. This work includes a discussion on the analysis to be done in order to choose the best configuration solution.

On the role of antigen in maintaining cytotoxic T-cell memory.

This study evaluated whether T-cell memory reflects increased precursor frequencies of specific long-lived T cells and/or a low-level immune response against some form of persistent antigen. Antivirally protective CD8+ T-cell memory was analyzed mostly in the original vaccinated host to assess the role of antigen in its maintenance. T-cell mediated resistance against reinfection was measured in the spleen and in peripheral solid organs with protocols that excluded protection by antibodies. In vivo protection was compared with detectable cytotoxic T-lymphocyte precursor frequencies determined in vitro. In the spleen, in vitro detectable cytotoxic T-lymphocyte precursor frequencies remained stable independently of antigen, conferring resistance against viral replication in the spleen during reinfection. In contrast, T-cell mediated resistance against reinfection of peripheral solid organs faded away in an antigen-dependent fashion within a few days or weeks. We show that only memory T cells persistently or freshly activated with antigen efficiently extravasate into peripheral organs, where cytotoxic T lymphocytes must be able to exert effector function immediately; both the capacity to extravasate and to rapidly exert effector function critically depend on restimulation by antigen. Our experiments document that the duration of T-cell memory protective against peripheral reinfection depended on the antigen dose used for immunization, was prolonged when additional antigen was provided, and was abrogated after removal of antigen. We conclude that T-cell mediated protective immunity against the usual peripheral routes of reinfection is antigen-dependent.

Short-term memory for emotional faces in dysphoria

The study aimed to determine if the memory bias for negative faces previously demonstrated in depression and dysphoria generalises from long- to short-term memory. A total of 29 dysphoric (DP) and22 non-dysphoric (ND) participants were presented with a series of faces and asked to identify the emotion portrayed (happiness, sadness, anger, or neutral affect). Following a delay, four faces were presented (the original plus three distractors) and participants were asked to identify the target face. Half of the trials assessed memory for facial emotion, and the remaining trials examined memory for facial identity. At encoding, no group differences were apparent. At memory testing, relative to ND participants, DP participants exhibited impaired memory for all types of facial emotion and for facial identity when the faces featured happiness, anger, or neutral affect, but not sadness. DP participants exhibited impaired identity memory for happy faces relative to angry, sad, and neutral, whereas ND participants exhibited enhanced facial identity memory when faces were angry. In general, memory for faces was not related to performance at encoding. However, in DP participants only, memory for sad faces was related to sadness recognition at encoding. The results suggest that the negative memory bias for faces in dysphoria does not generalise from long- to short-term memory.

Efficient middleware for database replication

Dissertação de Mestrado em Engenharia Informática

Arithmetic-based binary-to-RNS converter modulo {2(n)+/- k} for jn-Bit dynamic range

In this brief, a read-only-memoryless structure for binary-to-residue number system (RNS) conversion modulo {2(n) +/- k} is proposed. This structure is based only on adders and constant multipliers. This brief is motivated by the existing {2(n) +/- k} binary-to-RNS converters, which are particular inefficient for larger values of n. The experimental results obtained for 4n and 8n bits of dynamic range suggest that the proposed conversion structures are able to significantly improve the forward conversion efficiency, with an AT metric improvement above 100%, regarding the related state of the art. Delay improvements of 2.17 times with only 5% area increase can be achieved if a proper selection of the {2(n) +/- k} moduli is performed.