Locally oxidized silicon surface-plasmon Schottky detector for telecom regime.

We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip.

Locally-oxidized silicon surface-plasmon Schottky detector for telecom wavelengths

We demonstrate an integrated on-chip locally-oxidized silicon surface-plasmon Schottky detector for telecom wavelengths based on the internal photoemission process. Theoretical model and experimental results will be presented and discussed. © 2011 IEEE.

Locally oxidized silicon surface-plasmon Schottky detector for telecom regime

We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip. © 2011 American Chemical Society.

Locally-oxidized silicon surface-plasmon Schottky detector for telecom wavelengths

We demonstrate an integrated on-chip locally-oxidized silicon surface-plasmon Schottky detector for telecom wavelengths based on the internal photoemission process. Theoretical model and experimental results will be presented and discussed. © 2011 Optical Society of America.

Immobilization of Catalysts of Biological Interest on Porous Oxidized Silicon Surfaces

The present paper deals with the immobilization of redox mediators and proteins onto protected porous silicon surfaces to obtain their direct electrochemical reactions and to retain their bioactivities. This paper shows that MP-11 and viologens are able to establish chemical bonds with 3-aminopropyltriethoxylsilane-modified porous silicon surface. The functionalization of the surfaces have been fully characterized by energy dispersive X-ray analysis (EDX) and X-ray photoelectron spectroscopy (XPS) to examine the immobilization of these mediators onto the solid surface. Amperometric and open circuit potential measurements have shown the direct electron transfer between glucose oxidase and the electrode in the presence of the viologen mediator covalently linked to the 3-aminopropyltriethoxylsilane (APTES)-modified porous silicon surfaces.

Mono-crystalline silicon wafers manufactured by casting methods: Optoelectronic, structural and solar cell study

1) Introduction 2) The Quasi-mono, pseudo-mono, mono-like ERA. 3) Manufacturing mono-cast ingots: COST (seed recycling) 4) Summary and findings 5) Current status at DCWafers

Analysis of the Mechanical Properties of Multicrystalline and Monocrystalline Silicon Wafers Manufactured by Casting Methods

Quasi-monocrystalline silicon wafers have appeared as a critical innovation in the PV industry, joining the most favourable characteristics of the conventional substrates: the higher solar cell efficiencies of monocrystalline Czochralski-Si (Cz-Si) wafers and the lower cost and the full square-shape of the multicrystalline ones. However, the quasi-mono ingot growth can lead to a different defect structure than the typical Cz-Si process. Thus, the properties of the brand-new quasi-mono wafers, from a mechanical point of view, have been for the first time studied, comparing their strength with that of both Cz-Si mono and typical multicrystalline materials. The study has been carried out employing the four line bending test and simulating them by means of FE models. For the analysis, failure stresses were fitted to a three-parameter Weibull distribution. High mechanical strength was found in all the cases. The low quality quasi-mono wafers, interestingly, did not exhibit critical strength values for the PV industry, despite their noticeable density of extended defects.

Study of the brittle fracture of monocrystalline silicon wafers

There is a growing trend towards using thinner wafers in order to reduce the costs of solar energy. But the current tools employed during the solar cells production are not prepared to work with thinner wafers, decreasing the industrial yield due to the high number of wafers broken. To develop new tools, or modify existing ones, the mechanical properties have to be determined. This paper tackles an experimental study of the mechanical properties of wafers. First, the material characteristics are detailed and the process to obtain wafers is presented. Then, the complete test setup and the mechanical strength results interpreted by a described numerical model are shown.

Mechanical characterization of multicrystalline silicon wafers

The possibility of using more economical silicon feedstock, i.e. as support for epitaxial solar cells, is of interest when the cost reduction and the properties are attractive. We have investigated the mechanical behavior of two blocks of upgraded metallurgical silicon, which is known to present high content of impurities even after being purified by the directional solidification process. The impurities are mainly metals like Al and silicon compounds. Thus, it is important to characterize their effect in order to improve cell performance and to ensure the survival of the wafers throughout the solar value chain. Microstructure and mechanical properties were studied by means of ring on ring and three point bending tests. Additionally, Young’s modulus, hardness and fracture toughness were measured. These results showed that it is possible to obtain marked improvements in toughness when impurities act as microscopic internal crack arrestors. However, the same impurities can be initiators of damage due to residual thermal stresses introduced during the crystallization process.

The Influence of Different Surface Treatments on the Mechanical Strength of Silicon Wafers

The implementation of photovoltaic solar energy based on silicon is being slowed down by the shortage of raw material. In this context, the use of thinner wafers arises as a solution reducing the amount of silicon in the photovoltaic modules. On the other hand, the manufacturing process with thinner wafers can become complicated with traditional tools. The high number of damaged wafers reduces the global yield. It’s known that edge and surface cracks and defects determine the mechanical strength of wafers. There are several ways of removing these defects e. g. subjecting wafers to a mechanical polishing or to a chemical etching. This paper shows a comparison between different surface treatments and their influence on the mechanical strength.

Study of the Edge and Surface Cracks Influence in the Mechanical Strength of Silicon Wafers

The objective of the present study is the estimation of the depth to which the wire sawing process causes damage to the wafer surfaces. Previous analyses were carried out by means of the four line bending test. The characteristic of this test implied that the failure could be due to surface cracks located in the central zone of the wafer or near the edges. In order to evaluate the influence of the edge or surface cracks a new study has been carried out using the ball/ring on ring test. Description and results of the tests are presented. The preliminary analysis of the failure stress using analytical methods confirms the expected results. A Finite Element model developed to get more information of the test results is also presented.

Adsorption of silanes bearing nitrogenated Lewis bases on SiO 2/Si (100) model surfaces

The present paper describes the one-pot procedure for the formation of self-assembled thin films of two silanes on the model oxidized silicon wafer, SiO2/Si. SiO2/Si is a model system for other surfaces, such as glass, quartz, aerosol, and silica gel. MALDI-TOF MS with and without a matrix, XPS, and AFM have confirmed the formation of self-assembled thin films of both 3-imidazolylpropyltrimethoxysilane (3-IPTS) and 4-(N- propyltriethoxysilane-imino)pyridine (4-PTSIP) on the SiO2/Si surface after 30 min. Longer adsorption times lead to the deposition of nonreacted 3-IPTS precursors and the formation of agglomerates on the 3-IPTS monolayer. The formation of 4-PTSIP self-assembled layers on SiO2/Si is also demonstrated. The present results for the flat SiO2/Si surface can lead to a better understanding of the formation of a stationary phase for affinity chromatography as well as transition-metal-supported catalysts on silica and their relationship with surface roughness and ordering. The 3-IPTS and 4-PTSIP modified SiO2/Si wafers can also be envisaged as possible built-on-silicon thin-layer chromatography (TLC) extraction devices for metal determination or N-heterocycle analytes, such as histidine and histamine, with on-spot MALDI-TOF MS detection. © 2005 Elsevier Inc. All rights reserved.

Controllable chemical vapor deposition of large area uniform nanocrystalline graphene directly on silicon dioxide

Metal-catalyst-free chemical vapor deposition (CVD) of large area uniform nanocrystalline graphene on oxidized silicon substrates is demonstrated. The material grows slowly, allowing for thickness control down to monolayer graphene. The as-grown thin films are continuous with no observable pinholes, and are smooth and uniform across whole wafers, as inspected by optical-, scanning electron-, and atomic force microscopy. The sp 2 hybridized carbon structure is confirmed by Raman spectroscopy. Room temperature electrical measurements show ohmic behavior (sheet resistance similar to exfoliated graphene) and up to 13 of electric-field effect. The Hall mobility is ∼40 cm 2/Vs, which is an order of magnitude higher than previously reported values for nanocrystalline graphene. Transmission electron microscopy, Raman spectroscopy, and transport measurements indicate a graphene crystalline domain size ∼10 nm. The absence of transfer to another substrate allows avoidance of wrinkles, holes, and etching residues which are usually detrimental to device performance. This work provides a broader perspective of graphene CVD and shows a viable route toward applications involving transparent electrodes. © 2012 American Institute of Physics.