Impaired acuity of the approximate number system in 22q11.2 microdeletion syndrome

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

The real number system,

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An RNS based transform Architecture for H.264/AVC

This paper presents the architecture and the VHDL design of an integer 2-D DCT used in the H.264/AVC. The 2-D DCT computation is performed by exploiting it’s orthogonality and separability property. The symmetry of the forward and inverse transform is used in this implementation. To reduce the computation overhead for the addition, subtraction and multiplication operations, we analyze the suitability of carry-free position independent residue number system (RNS) for the implementation of 2-D DCT. The implementation has been carried out in VHDL for Altera FPGA. We used the negative number representation in RNS, bit width analysis of the transforms and dedicated registers present in the Logic element of the FPGA to optimize the area. The complexity and efficiency analysis show that the proposed architecture could provide higher through-put.

Divide-and-Correct Algorithm for Division in a Negative Base

A divide-and-correct algorithm is described for multiple-precision division in the negative base number system. In this algorithm an initial quotient estimate is obtained from suitable segmented operands; this is then corrected by simple rules to arrive at the true quotient.

Divide-and-Correct Algorithm for Division in a Negative Base

A divide-and-correct algorithm is described for multiple-precision division in the negative base number system. In this algorithm an initial quotient estimate is obtained from suitable segmented operands; this is then corrected by simple rules to arrive at the true quotient.

Deterministic Division Algorithm in a Negative Base

Described here is a deterministic division algorithm in a negative-base number system; here, the divisor is mapped into a suitable range by premultiplication, so that the choice of the quotient digit is deterministic.

Parallel optical negabinary arithmetic based on logic operations

On the basis of signed-digit negabinary representation, parallel two-step addition and one-step subtraction can be performed for arbitrary-length negabinary operands.; The arithmetic is realized by signed logic operations and optically implemented by spatial encoding and decoding techniques. The proposed algorithm and optical system are simple, reliable, and practicable, and they have the property of parallel processing of two-dimensional data. This leads to an efficient design for the optical arithmetic and logic unit. (C) 1997 Optical Society of America.

Parallel optical negabinary signed-digit computing: algorithm and optical implementation

Negabinary is a component of the positional number system. A complete set of negabinary arithmetic operations are presented, including the basic addition/subtraction logic, the two-step carry-free addition/subtraction algorithm based on negabinary signed-digit (NSD) representation, parallel multiplication, and the fast conversion from NSD to the normal negabinary in the carry-look-ahead mode. All the arithmetic operations can be performed with binary logic. By programming the binary reference bits, addition and subtraction can be realized in parallel with the same binary logic functions. This offers a technique to perform space-variant arithmetic-logic functions with space-invariant instructions. Multiplication can be performed in the tree structure and it is simpler than the modified signed-digit (MSD) counterpart. The parallelism of the algorithms is very suitable for optical implementation. Correspondingly, a general-purpose optical logic system using an electron trapping device is suggested. Various complex logic functions can be performed by programming the illumination of the data arrays without additional temporal latency of the intermediate results. The system can be compact. These properties make the proposed negabinary arithmetic-logic system a strong candidate for future applications in digital optical computing with the development of smart pixel arrays. (C) 1999 Society of Photo-Optical Instrumentation Engineers. [S0091-3286(99)00803-X].

Edukacyjne implikacje technologii cyfrowych

W ciągu minionych trzech dekad świat radykalnie się zmienił. Jesteśmy świadkami transformacji od społeczeństwa przemysłowego do społeczeństwa informacyjnego. Jeśli chcielibyśmy określić tą zmianę jednym słowem byłoby nim: cyfryzacja. Początkiem było wynalezienie cyfrowego komputera, a później wszystkie stare analogowe formy medialne (tekst, dźwięk, obraz, film) reprezentowane poprzez ciągłe (analogowe) sygnały zostały zastąpione przez nowe postaci cyfrowe. Pojęcie cyfrowy oznacza, że dowolne informacje mogą być reprezentowana w formie ciągów liczb zapisanych w dwójkowym systemie liczbowym (jako ciąg znaków: 0 i 1). W artykule pokazujemy funkcjonalne ograniczenia mediów analogowych oraz rozważamy korzyści wynikające z cyfrowych reprezentacji różnych form informacji wskazując równocześnie zmiany jakie implikuje to dla procesu uczenia się i edukacji.

Programmable high-performance IIR filter chip

The paper presents a state-of-the-art commercial demonstrator chip for infinite impulse response (IIR) filtering. The programmable IIR filter chip contains eight multiplier/accumulators that can be configured in one of five different modes to implement up to a 16th-order IIR filter. The multiply-accumulate block is based on a highly regular systolic array architecture and uses a redundant number system to overcome problems of pipelining in the feedback loop. The chip has been designed using the GEC Plessey Semiconductors CLA 78000 series gate array, operates on 16-bit two's complement data and has a clock speed of 30 MHz. Issues such as overflow detection and design for testability have also been addressed and are described.

Relatório de estágio

Resumo I (Prática Pedagógica) - O Estágio do Ensino Especializado realizado no presente ano lectivo foi elaborado na Academia de Música de Lisboa em três turmas. Vários foram os desafios encontrados no decorrer do ano lectivo, como por exemplo a instabilidade das turmas, a falta do quadro na sala em algumas aulas e a pouca experiência anterior na área de docência. A realização deste estágio permitiu experimentar actividades e estratégias aprendidas nas disciplinas do mestrado e estimulou uma atitude de reflexão regular sobre as escolhas pedagógicas elaboradas e sobre a resposta dos alunos. Também o feedback dos professores da Unidade Curricular de Didáctica do Ensino Especializado foi essencial na consciencialização de aspectos que teriam que ser mudados na minha abordagem do ensino: fazer actividades mais formativas e menos avaliativas, dar mais feedback, não avançar para outro nível enquanto uma tarefa ainda não estiver consolidada, não modificar as instruções tão rapidamente, ter cuidado com a apresentação visual das células rítmicas e pensar em soluções para quando os alunos estão cansados. Foi também importante reflectir sobre os planos de aula realizados ao longo do ano e sobre o que não seria realizado da mesma forma, nomeadamente na introdução de células rítmicas, introdução de funções harmónicas e cadências. Durante este ano foi feito um esforço para melhorar estes aspectos, no entanto ainda não foi possível implementar todas as mudanças. De qualquer modo, esta reflexão é um bom ponto de partida para o planeamento do próximo ano e um exemplo da atitude que deve acompanhar-me durante toda a minha actividade enquanto docente.

Le développement d’une séquence d’enseignement/apprentissage basée sur l’histoire de la numération pour des élèves du troisième cycle du primaire

Notre contexte pratique — nous enseignons à des élèves doués de cinquième année suivant le programme international — a grandement influencé la présente recherche. En effet, le Programme primaire international (Organisation du Baccalauréat International, 2007) propose un enseignement par thèmes transdisciplinaires, dont un s’intitulant Où nous nous situons dans l’espace et le temps. Aussi, nos élèves sont tenus de suivre le Programme de formation de l’école québécoise (MÉLS Ministère de l'Éducation du Loisir et du Sport, 2001) avec le développement, notamment, de la compétence Résoudre une situation-problème et l’introduction d’une nouveauté : les repères culturels. Après une revue de la littérature, l’histoire des mathématiques nous semble tout indiquée. Toutefois, il existe peu de ressources pédagogiques pour les enseignants du primaire. Nous proposons donc d’en créer, nous appuyant sur l’approche constructiviste, approche prônée par nos deux programmes d’études (OBI et MÉLS). Nous relevons donc les avantages à intégrer l’histoire des mathématiques pour les élèves (intérêt et motivation accrus, changement dans leur façon de percevoir les mathématiques et amélioration de leurs apprentissages et de leur compréhension des mathématiques). Nous soulignons également les difficultés à introduire une approche historique à l’enseignement des mathématiques et proposons diverses façons de le faire. Puis, les concepts mathématiques à l’étude, à savoir l’arithmétique, et la numération, sont définis et nous voyons leur importance dans le programme de mathématiques du primaire. Nous décrivons ensuite les six systèmes de numération retenus (sumérien, égyptien, babylonien, chinois, romain et maya) ainsi que notre système actuel : le système indo-arabe. Enfin, nous abordons les difficultés que certaines pratiques des enseignants ou des manuels scolaires posent aux élèves en numération. Nous situons ensuite notre étude au sein de la recherche en sciences de l’éducation en nous attardant à la recherche appliquée ou dite pédagogique et plus particulièrement aux apports des recherches menées par des praticiens (un rapprochement entre la recherche et la pratique, une amélioration de l’enseignement et/ou de l’apprentissage, une réflexion de l’intérieur sur la pratique enseignante et une meilleure connaissance du milieu). Aussi, nous exposons les risques de biais qu’il est possible de rencontrer dans une recherche pédagogique, et ce, pour mieux les éviter. Nous enchaînons avec une description de nos outils de collecte de données et rappelons les exigences de la rigueur scientifique. Ce n’est qu’ensuite que nous décrivons notre séquence d’enseignement/apprentissage en détaillant chacune des activités. Ces activités consistent notamment à découvrir comment différents systèmes de numération fonctionnent (à l’aide de feuilles de travail et de notations anciennes), puis comment ces mêmes peuples effectuaient leurs additions et leurs soustractions et finalement, comment ils effectuaient les multiplications et les divisions. Enfin, nous analysons nos données à partir de notre journal de bord quotidien bonifié par les enregistrements vidéo, les affiches des élèves, les réponses aux tests de compréhension et au questionnaire d’appréciation. Notre étude nous amène à conclure à la pertinence de cette séquence pour notre milieu : l’intérêt et la motivation suscités, la perception des mathématiques et les apprentissages réalisés. Nous revenons également sur le constructivisme et une dimension non prévue : le développement de la communication mathématique.

Secret Sharing Schemes Using Visual Cryptography

Secret sharing schemes allow a secret to be shared among a group of participants so that only qualified subsets of participants can recover the secret. A visual cryptography scheme (VCS) is a special kind of secret sharing scheme in which the secret to share consists of an image and the shares consist of xeroxed transparencies which are stacked to recover the shared image. In this thesis we have given the theoretical background of Secret Sharing Schemes and the historical development of the subject. We have included a few examples to improve the readability of the thesis. We have tried to maintain the rigor of the treatment of the subject. The limitations and disadvantages of the various forms secret sharing schemes are brought out. Several new schemes for both dealing and combining are included in the thesis. We have introduced a new number system, called, POB number system. Representation using POB number system has been presented. Algorithms for finding the POB number and POB value are given.We have also proved that the representation using POB number system is unique and is more efficient. Being a new system, there is much scope for further development in this area.

Efficient Transmitter/Receiver Architectures for High Performance Wireless Applications

The thesis focuses on efficient design methods and reconfiguration architectures suitable for higher performance wireless communication .The work presented in this thesis describes the development of compact,inexpensive and low power communication devices that are robust,testable and capable of handling multiple communication standards.A new multistandard Decimation Filter Design Toolbox is developed in MATLAB GUIDE environment.RNS based dual-mode decimation filters reconfigurable for WCDMA/WiMAX and WCDMA/WLANa standards are designed and implemented.It offers high speed operation with lesser area requirement and lower dynamic power dissipation.A novel sigma-delta based direct analog-to-residue converter that reduces the complexity of RNS conversion circuitry is presented.The performance of an OFDM communication system with a new RRNS-convolutional concatenated coding is analysed and improved BER performance is obtained under different channel conditions. Easily testable MAC units for filters are presented using Reed-Muller logic for realization.

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.