On Space-Time Trade-Off for Montgomery Multipliers over Finite Fields

La multiplication dans le corps de Galois à 2^m éléments (i.e. GF(2^m)) est une opérations très importante pour les applications de la théorie des correcteurs et de la cryptographie. Dans ce mémoire, nous nous intéressons aux réalisations parallèles de multiplicateurs dans GF(2^m) lorsque ce dernier est généré par des trinômes irréductibles. Notre point de départ est le multiplicateur de Montgomery qui calcule A(x)B(x)x^(-u) efficacement, étant donné A(x), B(x) in GF(2^m) pour u choisi judicieusement. Nous étudions ensuite l'algorithme diviser pour régner PCHS qui permet de partitionner les multiplicandes d'un produit dans GF(2^m) lorsque m est impair. Nous l'appliquons pour la partitionnement de A(x) et de B(x) dans la multiplication de Montgomery A(x)B(x)x^(-u) pour GF(2^m) même si m est pair. Basé sur cette nouvelle approche, nous construisons un multiplicateur dans GF(2^m) généré par des trinôme irréductibles. Une nouvelle astuce de réutilisation des résultats intermédiaires nous permet d'éliminer plusieurs portes XOR redondantes. Les complexités de temps (i.e. le délais) et d'espace (i.e. le nombre de portes logiques) du nouveau multiplicateur sont ensuite analysées: 1. Le nouveau multiplicateur demande environ 25% moins de portes logiques que les multiplicateurs de Montgomery et de Mastrovito lorsque GF(2^m) est généré par des trinômes irréductible et m est suffisamment grand. Le nombre de portes du nouveau multiplicateur est presque identique à celui du multiplicateur de Karatsuba proposé par Elia. 2. Le délai de calcul du nouveau multiplicateur excède celui des meilleurs multiplicateurs d'au plus deux évaluations de portes XOR. 3. Nous determinons le délai et le nombre de portes logiques du nouveau multiplicateur sur les deux corps de Galois recommandés par le National Institute of Standards and Technology (NIST). Nous montrons que notre multiplicateurs contient 15% moins de portes logiques que les multiplicateurs de Montgomery et de Mastrovito au coût d'un délai d'au plus une porte XOR supplémentaire. De plus, notre multiplicateur a un délai d'une porte XOR moindre que celui du multiplicateur d'Elia au coût d'une augmentation de moins de 1% du nombre total de portes logiques.

Accelerating Reduction for Enabling Fast Multiplication over Large Binary Fields

In this paper we present a hardware-software hybrid technique for modular multiplication over large binary fields. The technique involves application of Karatsuba-Ofman algorithm for polynomial multiplication and a novel technique for reduction. The proposed reduction technique is based on the popular repeated multiplication technique and Barrett reduction. We propose a new design of a parallel polynomial multiplier that serves as a hardware accelerator for large field multiplications. We show that the proposed reduction technique, accelerated using the modified polynomial multiplier, achieves significantly higher performance compared to a purely software technique and other hybrid techniques. We also show that the hybrid accelerated approach to modular field multiplication is significantly faster than the Montgomery algorithm based integrated multiplication approach.

Optical techniques for real-time binary multiplication

An optical system which performs the multiplication of binary numbers is described and proof-of-principle experiments are performed. The simultaneous generation of all partial products, optical regrouping of bit products, and optical carry look-ahead addition are novel features of the proposed scheme which takes advantage of the parallel operations capability of optical computers. The proposed processor uses liquid crystal light valves (LCLVs). By space-sharing the LCLVs one such system could function as an array of multipliers. Together with the optical carry look-ahead adders described, this would constitute an optical matrix-vector multiplier.

Tissue culture of forest trees: Clonal multiplication of Eucalyptus grandis L

Axillary shoot proliferation was obtained using explants of Eucalyptus grandis L. juvenile and mature stages on a defined medium. Murashige and Skoog medium (MS) supplemented with benzyladenine (BA), naphthalene acetic acid (NAA) and additional thiamine. Excised shoots were induced to root on a sequence of three media: (1) White's medium containing indoleacetic acid (IAA), NAA and indole butyric acid; (IBA), (2) half-strength MS medium with charcoal and (3) half-strength MS liquid medium. The two types of explants differed in rooting response, with juvenile-derived shoots giving 60% rooting and adult-derived ones only 35%. Thus, the factors limiting cloning of selected trees in vitro are determined to be those controlling rooting of shoots in E. grandis.

Multiplication of hybrid aspen (Populus tremula L. x P. tremuloides Michx.) from cuttings

The primary aim of the present study was to find an efficient and simple method of vegetative propagation for producing large numbers of hybrid aspen (Populus tremuloides L. x P. tremula Michx.) plants for forest plantations. The key objectives were to investigate the main physiological factors that affect the ability of cuttings to regenerate and to determine whether these factors could be manipulated by different growth conditions. In addition, clonal variation in traits related to propagation success was examined. According to our results, with the stem cutting method, depending on the clone, it is possible to obtain only 1−8 plants from one stock plant per year. With the root cutting method the corresponding values for two-year-old stock plants are 81−207 plants. The difference in number of cuttings between one- and two-year-old stock plants is so pronounced that it is economically feasible to grow stock plants for two years. There is no reason to use much older stock plants as a source of cuttings, as it has been observed that rooting ability diminishes as root diameter increases. Clonal variation is the most important individual factor in propagation of hybrid aspen. The fact that the efficiently sprouted clones also rooted best facilitates the selection of clones for large-scale propagation. In practice, root cuttings taken from all parts of the root system of hybrid aspen were capable of producing new shoots and roots. However, for efficient rooting it is important to use roots smaller than one centimeter in diameter. Both rooting and sprouting, as well as sprouting rate, were increased by high soil temperature; in our studies the highest temperature tested (30ºC) was the best. Light accelerated the sprouting of root cuttings, but they rooted best in dark conditions. Rooting is essential because without roots the sprouted cutting cannot survive long. For aspen the criteria for clone selection are primarily fiber qualities and growth rate, but ability to regenerate efficiently is also essential. For large-scale propagation it is very important to find clones from which many cuttings per stock plant can be obtained. In light of production costs, however, it is even more important that the regeneration ability of the produced cuttings be high.

Quadrature generation techniques for frequency multiplication based oscillators

Frequency multiplication (FM) can be used to design low power frequency synthesizers. This is achieved by running the VCO at a much reduced frequency, while employing a power efficient frequency multiplier, and also thereby eliminating the first few dividers. Quadrature signals can be generated by frequency- multiplying low frequency I/Q signals, however this also multiplies the quadrature error of these signals. Another way is generating additional edges from the low-frequency oscillator (LFO) and develop a quadrature FM. This makes the I-Q precision heavily dependent on process mismatches in the ring oscillator. In this paper we examine the use of fewer edges from LFO and a single stage polyphase filter to generate approximate quadrature signals, which is then followed by an injection-locked quadrature VCO to generate high- precision I/Q signals. Simulation comparisons with the existing approach shows that the proposed method offers very good phase accuracy of 0.5deg with only a modest increase in power dissipation for 2.4 GHz IEEE 802.15.4 standard using UMC 0.13 mum RFCMOS technology.

Pipelined ring algorithm for matrix multiplication on transputer networks: performance analysis and estimation

A parallel matrix multiplication algorithm is presented, and studies of its performance and estimation are discussed. The algorithm is implemented on a network of transputers connected in a ring topology. An efficient scheme for partitioning the input matrices is introduced which enables overlapping computation with communication. This makes the algorithm achieve near-ideal speed-up for reasonably large matrices. Analytical expressions for the execution time of the algorithm have been derived by analysing its computation and communication characteristics. These expressions are validated by comparing the theoretical results of the performance with the experimental values obtained on a four-transputer network for both square and irregular matrices. The analytical model is also used to estimate the performance of the algorithm for a varying number of transputers and varying problem sizes. Although the algorithm is implemented on transputers, the methodology and the partitioning scheme presented in this paper are quite general and can be implemented on other processors which have the capability of overlapping computation with communication. The equations for performance prediction can also be extended to other multiprocessor systems.

Hardware implementation of 4x4 DCT/Quantization block using multiplication and error-free algorithm

The 4ÃÂ4 discrete cosine transform is one of the most important building blocks for the emerging video coding standard, viz. H.264. The conventional implementation does some approximation to the transform matrix elements to facilitate integer arithmetic, for which hardware is suitably prepared. Though the transform coding does not involve any multiplications, quantization process requires sixteen 16-bit multiplications. The algorithm used here eliminates the process of approximation in transform coding and multiplication in the quantization process, by usage of algebraic integer coding. We propose an area-efficient implementation of the transform and quantization blocks based on the algebraic integer coding. The designs were synthesized with 90 nm TSMC CMOS technology and were also implemented on a Xilinx FPGA. The gate counts and throughput achievable in this case are 7000 and 125 Msamples/sec.

A Low Power Frequency Multiplication Technique for Zigbee Transceiver

A low-power frequency multiplication technique, developed for ZigBee (IEEE 802.15.4) like applications is presented. We have provided an estimate for the power consumption for a given output voltage swing using our technique. The advantages and disadvantages which determine the application areas of the technique are discussed. The issues related to design, layout and process variation are also addressed. Finally, a design is presented for operation in 2.405-2.485-GHz band of ZigBee receiver. SpectreRF simulations show 30% improvement in efficiency for our circuit with regard to conversion of DC bias current to output amplitude, against a LC-VCO. To establish the low-power credentials, we have compared our circuit with an existing technique; our circuit performs better with just 1/3 of total current from supply, and uses one inductor as against three in the latter case. A test chip was implemented in UMC 0.13-mum RF process with spiral on-chip inductors and MIM (metal-insulator-metal) capacitor option.

A Digital Frequency Multiplication Technique for Energy Efficient Transmitters

A logic gate-based digital frequency multiplication technique for low-power frequency synthesis is presented. The proposed digital edge combining approach offers broadband operation with low-power and low-area advantages and is a promising candidate for low-power frequency synthesis in deep submicrometer CMOS technologies. Chip prototype of the proposed frequency multiplication-based 2.4-GHz binary frequency-shift-keying (BFSK)/amplitude shift keying (ASK) transmitter (TX) was fabricated in 0.13-mu m CMOS technology. The TX achieves maximum data rates of 3 and 20 Mb/s for BFSK and ASK modulations, respectively, consuming a 14-mA current from 1.3 V supply voltage. The corresponding energy efficiencies of the TX are 3.6 nJ/bit for BFSK and 0.91 nJ/bit for ASK modulations.

Optical fringe multiplication technique with TEM nano-moiré method

In this paper, a nano-moiré fringe multiplication method is proposed, which can be used to measure nano-deformation of single crystal materials. The lattice structure of Si (111) is recorded on a film at a given magnification under a transmission microscope, which acts as a specimen grating. A parallel grating (binary type) on glass or film is selected as a reference grating. A multiplied nano-moiré fringe pattern can be reproduced in a 4f optical filter system with the specimen grating and the prepared reference grating. The successful results illustrate that this method can be used to measure deformation in nanometre scale. The method is especially useful in the measurement of the inhomogeneous displacement field, and can be utilized to characterize nano-mechanical behaviour of materials such as dislocation and atomic bond failure.