Junctionless Multiple-Gate Transistors for Analog Applications

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width W(fin) and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage V(EA) and larger intrinsic voltage gain A(V) than IM devices of similar dimensions. In addition, V(EA) and A(V) are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.

Simulations of parasitic and intrinsic capacitances related to Multiple-Gate-Field-Effect Transistor architectures

Report for the scientific sojourn carried out at the Université Catholique de Louvain, Belgium, from March until June 2007. In the first part, the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET) is deeply analyzed using finite element simulations. Several architectures such as single gate, FinFETs (double gate), triple-gate represented by Pi-gate MOSFETs are simulated and compared in terms of channel and fringing capacitances for the same occupied die area. Simulations highlight the great impact of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when Selective Epitaxial Growth (SEG) technology is introduced. The impact of these technological solutions on the transistor cut-off frequencies is also discussed. The second part deals with the study of the effect of the volume inversion (VI) on the capacitances of undoped Double-Gate (DG) MOSFETs. For that purpose, we present simulation results for the capacitances of undoped DG MOSFETs using an explicit and analytical compact model. It monstrates that the transition from volume inversion regime to dual gate behaviour is well simulated. The model shows an accurate dependence on the silicon layer thickness,consistent withtwo dimensional numerical simulations, for both thin and thick silicon films. Whereas the current drive and transconductance are enhanced in volume inversion regime, our results show thatintrinsic capacitances present higher values as well, which may limit the high speed (delay time) behaviour of DG MOSFETs under volume inversion regime.

Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects

The progresses of electron devices integration have proceeded for more than 40 years following the well–known Moore’s law, which states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face them. In order to overcome the limitations related to conventional structures, the researchers community is preparing different solutions, that need to be assessed. Possible solutions currently under scrutiny are represented by: • devices incorporating materials with properties different from those of silicon, for the channel and the source/drain regions; • new architectures as Silicon–On–Insulator (SOI) transistors: the body thickness of Ultra-Thin-Body SOI devices is a new design parameter, and it permits to keep under control Short–Channel–Effects without adopting high doping level in the channel. Among the solutions proposed in order to overcome the difficulties related to scaling, we can highlight heterojunctions at the channel edge, obtained by adopting for the source/drain regions materials with band–gap different from that of the channel material. This solution allows to increase the injection velocity of the particles travelling from the source into the channel, and therefore increase the performance of the transistor in terms of provided drain current. The first part of this thesis work addresses the use of heterojunctions in SOI transistors: chapter 3 outlines the basics of the heterojunctions theory and the adoption of such approach in older technologies as the heterojunction–bipolar–transistors; moreover the modifications introduced in the Monte Carlo code in order to simulate conduction band discontinuities are described, and the simulations performed on unidimensional simplified structures in order to validate them as well. Chapter 4 presents the results obtained from the Monte Carlo simulations performed on double–gate SOI transistors featuring conduction band offsets between the source and drain regions and the channel. In particular, attention has been focused on the drain current and to internal quantities as inversion charge, potential energy and carrier velocities. Both graded and abrupt discontinuities have been considered. The scaling of devices dimensions and the adoption of innovative architectures have consequences on the power dissipation as well. In SOI technologies the channel is thermally insulated from the underlying substrate by a SiO2 buried–oxide layer; this SiO2 layer features a thermal conductivity that is two orders of magnitude lower than the silicon one, and it impedes the dissipation of the heat generated in the active region. Moreover, the thermal conductivity of thin semiconductor films is much lower than that of silicon bulk, due to phonon confinement and boundary scattering. All these aspects cause severe self–heating effects, that detrimentally impact the carrier mobility and therefore the saturation drive current for high–performance transistors; as a consequence, thermal device design is becoming a fundamental part of integrated circuit engineering. The second part of this thesis discusses the problem of self–heating in SOI transistors. Chapter 5 describes the causes of heat generation and dissipation in SOI devices, and it provides a brief overview on the methods that have been proposed in order to model these phenomena. In order to understand how this problem impacts the performance of different SOI architectures, three–dimensional electro–thermal simulations have been applied to the analysis of SHE in planar single and double–gate SOI transistors as well as FinFET, featuring the same isothermal electrical characteristics. In chapter 6 the same simulation approach is extensively employed to study the impact of SHE on the performance of a FinFET representative of the high–performance transistor of the 45 nm technology node. Its effects on the ON–current, the maximum temperatures reached inside the device and the thermal resistance associated to the device itself, as well as the dependence of SHE on the main geometrical parameters have been analyzed. Furthermore, the consequences on self–heating of technological solutions such as raised S/D extensions regions or reduction of fin height are explored as well. Finally, conclusions are drawn in chapter 7.

Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs

The impact of the titanium nitride (TIN) gate electrode thickness has been investigated in n and p channel SOI multiple gate field effect transistors (MuGFETs) through low frequency noise charge pumping and static measurements as well as capacitance-voltage curves The results suggest that a thicker TIN metal gate electrode gives rise to a higher EOT a lower mobility and a higher interface trap density The devices have also been studied for different back gate biases where the GIFBE onset occurs at lower front-gate voltage for thinner TIN metal gate thickness and at higher V(GF) In addition it is demonstrated that post deposition nitridation of the MOCVD HfSiO gate dielectric exhibits an unexpected trend with TIN gate electrode thickness where a continuous variation of EOT and an increase on the degradation of the interface quality are observed (C) 2010 Elsevier Ltd All rights reserved

Influence of the sidewall crystal orientation, HfSiO nitridation and TiN metal gate thickness on n-MuGFETs under analog operation

This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high-k post-nitridation. TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high-k material is subjected to a nitridation step indicated a degradation of the Early voltage (V(EA)) values which resulted in a lower voltage gain. The 45 degrees rotated devices have a smaller V(EA) than the standard ones when a HfSiO dielectric is used. However, the higher transconductance of these devices, due to the increased mobility in the (1 0 0) sidewall orientation, compensates this V(EA) degradation of the voltage gain, keeping it nearly equal to the voltage gain values of the standard devices. (C) 2011 Elsevier Ltd. All rights reserved.

GIDL behavior of p- and n-MuGFET devices with different TiN metal gate thickness and high-k gate dielectrics

This work studies the gate-induced drain leakage (GIDL) in p- and n-MuGFET structures with different TiN metal gate thickness and high-k gate dielectrics. As a result of this analysis, it was observed that a thinner TiN metal gate showed a larger GIDL due to the different gate oxide thickness and a reduced metal gate work function. In addition, replacing SiON by a high-k dielectric (HfSiON) results for nMuGFETs in a decrease of the GIDL On the other hand, the impact of the gate dielectric on the GIDL for p-channel MuGFETs is marginal. The effect of the channel width was also studied, whereby narrow fin devices exhibit a reduced GIDL current in spite of the larger vertical electric field expected for these devices. Finally, comparing the effect of the channel type, an enhanced GIDL current for pMuGFET devices was observed. (C) 2011 Elsevier Ltd. All rights reserved.

Threshold voltages of SOI MuGFETs

The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. (C) 2008 Elsevier Ltd. All rights reserved.

Uniaxial and/or Biaxial Strain Influence on MuGFET Devices

In this work, the impact of global and/or local strain engineering techniques on tri-gate p- and nMuGFETs performance is experimentally evaluated. Multiple gate structures were analyzed through basic and analog performance parameters for four different splits processed with different strain-engineering techniques (unstrained, uniaxial, biaxial and uniaxial+biaxial stress). While n-channel devices with narrow fins present a worse analog behavior, biaxial stress promotes the electron mobility for larger devices increasing the voltage gain. Besides the voltage gain, the transconductance, output conductance and Early Voltage are also evaluated. Although pMuGFETs are less affected by the strain engineering, they present better analog behavior for all studied devices.

Influence of 60-MeV Proton-Irradiation on Standard and Strained n- and p-Channel MuGFETs

In this work the proton irradiation influence on Multiple Gate MOSFETs (MuGFETs) performance is investigated. This analysis was performed through basic and analog parameters considering four different splits (unstrained, uniaxial, biaxial, uniaxial+biaxial). Although the influence of radiation is more pronounced for p-channel devices, in pMuGFETs devices, the radiation promotes a higher immunity to the back interface conduction resulting in the analog performance improvement. On the other hand, the proton irradiation results in a degradation of the post-irradiated n-channel transistors behavior. The unit gain frequency showed to be strongly dependent on stress efficiency and the radiation results in an increase of the unit gain frequency for splits with high stress effectiveness for both cases p- and nMuGFETs.

Protonation controls ASIC1a activity via coordinated movements in multiple domains.

Acid-sensing ion channels (ASICs) are neuronal Na(+)-conducting channels activated by extracellular acidification. ASICs are involved in pain sensation, expression of fear, and neurodegeneration after ischemic stroke. Functional ASICs are composed of three identical or homologous subunits, whose extracellular part has a handlike structure. Currently, it is unclear how protonation of residues in extracellular domains controls ASIC activity. Knowledge of these mechanisms would allow a rational development of drugs acting on ASICs. Protonation may induce conformational changes that control the position of the channel gate. We used voltage-clamp fluorometry with fluorophores attached to residues in different domains of ASIC1a to detect conformational changes. Comparison of the timing of fluorescence and current signals identified residues involved in movements that preceded desensitization and may therefore be associated with channel opening or early steps leading to desensitization. Other residues participated in movements intimately linked to desensitization and recovery from desensitization. Fluorescence signals of all mutants were detected at more alkaline pH than ionic currents. Their midpoint of pH dependence was close to that of steady-state desensitization, whereas the steepness of the pH fluorescence relationship was closer to that of current activation. A sequence of movements was observed upon acidification, and its backward movements during recovery from desensitization occurred in the reverse order, indicating that the individual steps are interdependent. Furthermore, the fluorescence signal of some labeled residues in the finger domain was strongly quenched by a Trp residue in the neighboring β-ball domain. Upon channel activation, their fluorescence intensity increased, indicating that the finger moved away from the β ball. This extensive analysis of activity-dependent conformational changes in ASICs sheds new light on the mechanisms by which protonation controls ASIC activity.

(Table S1) Flux gate discharge and centerline discharge of Helheim, Kangerdlugssuaq and Jakobshavn glacier, Greenland

Acceleration of Greenland's three largest outlet glaciers, Helheim, Kangerdlugssuaq and Jakobshavn Isbræ, accounted for a substantial portion of the ice sheet's mass loss over the past decade. Rapid changes in their discharge, however, make their cumulative mass-change uncertain. We derive monthly mass balance rates and cumulative balance from discharge and surface mass balance (SMB) rates for these glaciers from 2000 through 2010. Despite the dramatic changes observed at Helheim, the glacier gained mass over the period, due primarily to the short duration of acceleration and a likely longer-term positive balance. In contrast, Jakobshavn Isbræ lost an equivalent of over 11 times the average annual SMB and loss continues to accelerate. Kangerdlugssuaq lost over 7 times its annual average SMB, but loss has returned to the 2000 rate. These differences point to contrasts in the long-term evolution of these glaciers and the danger in basing predictions on extrapolations of recent changes.

Scaling of multiple postselected quantum gates in optics

We show that interesting multigate circuits can be constructed using a postselected controlled-sign gate that works with a probability (1/3)(n), where n-1 is the number of controlled-sign gates in the circuit, rather than (1/9)(n-1), as would be expected from a sequence of such gates. We suggest some quantum information tasks which could be demonstrated using these circuits, such as parity checking and cluster-state computation.

The Clinical Impact Of Cerebellar Grey Matter Pathology In Multiple Sclerosis.

The cerebellum is an important site for cortical demyelination in multiple sclerosis, but the functional significance of this finding is not fully understood. To evaluate the clinical and cognitive impact of cerebellar grey-matter pathology in multiple sclerosis patients. Forty-two relapsing-remitting multiple sclerosis patients and 30 controls underwent clinical assessment including the Multiple Sclerosis Functional Composite, Expanded Disability Status Scale (EDSS) and cerebellar functional system (FS) score, and cognitive evaluation, including the Paced Auditory Serial Addition Test (PASAT) and the Symbol-Digit Modalities Test (SDMT). Magnetic resonance imaging was performed with a 3T scanner and variables of interest were: brain white-matter and cortical lesion load, cerebellar intracortical and leukocortical lesion volumes, and brain cortical and cerebellar white-matter and grey-matter volumes. After multivariate analysis high burden of cerebellar intracortical lesions was the only predictor for the EDSS (p<0.001), cerebellar FS (p = 0.002), arm function (p = 0.049), and for leg function (p<0.001). Patients with high burden of cerebellar leukocortical lesions had lower PASAT scores (p = 0.013), while patients with greater volumes of cerebellar intracortical lesions had worse SDMT scores (p = 0.015). Cerebellar grey-matter pathology is widely present and contributes to clinical dysfunction in relapsing-remitting multiple sclerosis patients, independently of brain grey-matter damage.

Multiple Desmoid Tumors In A Patient With Gardner's Syndrome - Report Of A Case.

Desmoid tumor (DT) is a common manifestation of Gardner's Syndrome (GS), although it is a rare condition in the general population. DT in patients with GS is usually located in the abdominal wall and/or intra-abdominal cavity. We report a case of a 32 years-old female patient with familial adenomatous polyposis (FAP), who was already submitted to total colectomy and developed multiple DT, located in the abdominal wall and in the left breast. The patient underwent several surgical procedures, with a multidisciplinary team of surgeons. Wide surgical resections of the left breast and the abdominal wall tumors were performed in separate steps. Polypropylene mesh reconstruction and muscle flaps were needed to cover the defects of the thoracic and abdominal walls. After partial necrosis of the adipose-cutaneous flap in the abdomen that required a new skin graft, she had a satisfactory outcome with complete healing of the surgical incisions. DT is frequent in GS, however, breast localization is very rare, with few cases reported in the literature. Recurrence of DT is not negligible, even after a wide surgical resection. GS patients must be followed up closely, and clinical examination, associated with imaging studies, should be performed to detect any signs of tumor. DT represents one of the most significant causes of the morbidity and mortality that affects FAP patients following colectomy. In general, the surgical procedures to excise DT are highly complex, requiring a multidisciplinary team.

The Effect Of Pelvic Floor Muscle Training Alone Or In Combination With Electrostimulation In The Treatment Of Sexual Dysfunction In Women With Multiple Sclerosis.

Sexual dysfunction (SD) affects up to 80% of multiple sclerosis (MS) patients and pelvic floor muscles (PFMs) play an important role in the sexual function of these patients. The objective of this paper is to evaluate the impact of a rehabilitation program to treat lower urinary tract symptoms on SD of women with MS. Thirty MS women were randomly allocated to one of three groups: pelvic floor muscle training (PFMT) with electromyographic (EMG) biofeedback and sham neuromuscular electrostimulation (NMES) (Group I), PFMT with EMG biofeedback and intravaginal NMES (Group II), and PFMT with EMG biofeedback and transcutaneous tibial nerve stimulation (TTNS) (Group III). Assessments, before and after the treatment, included: PFM function, PFM tone, flexibility of the vaginal opening and ability to relax the PFMs, and the Female Sexual Function Index (FSFI) questionnaire. After treatment, all groups showed improvements in all domains of the PERFECT scheme. PFM tone and flexibility of the vaginal opening was lower after the intervention only for Group II. All groups improved in arousal, lubrication, satisfaction and total score domains of the FSFI questionnaire. This study indicates that PFMT alone or in combination with intravaginal NMES or TTNS contributes to the improvement of SD.