Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS

This work investigates the harmonic distortion (HD) in 2-MOS balanced structures composed of triple gate FinFETs. HD has been evaluated through the determination of the third-order harmonic distortion (HD3), since this represents the major non-linearity source in balanced structures. The 2-MOS structures with devices of different channel lengths (L) and fin widths (W(fin)) have been studied operating in the linear region as tunable resistors. The analysis was performed as a function of the gate voltage, aiming to verify the correlation between operation bias and HD3. The physical origins of the non-linearities have been investigated and are pointed out. Being a resistive circuit, the 2-MOS structure is generally projected for a targeted on-resistance, which has also been evaluated in terms of HD3. The impact of the application of biaxial strain has been studied for FinFETs of different dimensions. It has been noted that HD3 reduces with the increase of the gate bias for all the devices and this reduction is more pronounced both in narrower and in longer devices. Also, the presence of strain slightly diminishes the non-linearity at a similar bias. However, a drawback associated with the use of strain engineering consists in a significant reduction of the on-resistance with respect to unstrained devices. (C) 2011 Elsevier Ltd. All rights reserved.

A new method of threshold voltage extraction via MOSFET gate-to-substrate capacitance measurement

A new method to extract MOSFET's threshold voltage VT by measurement of the gate-to-substrate capacitance C-gb of the transistor is presented. Unlike existing extraction methods based on I-V data, the measurement of C-gb does not require de drain current to now between drain and source thus eliminating the effects of source and drain series resistance R-S/D, and at the same time, retains a symmetrical potential profile across the channel. Experimental and simulation results on devices with different sizes are presented to justify the proposed method.

High-performance L-band series and parallel switches using low-cost p-i-n diodes

Low-cost UHF-band p-i-n diodes are used to develop high-performance L-band series and parallel switches. To stop the rectification of large RF, signals, the diodes are biased at a large reverse-bias voltage. Parasitic elements of the diodes are tuned out using LC circuits in biasing circuits without increasing the size of the switches. (C) 2002 John Wiley Sons, Inc.

Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.

Schedulability analysis of generalized multiframe traffic on multihop-networks comprising software-implemented ethernet switches

Consider a multihop network comprising Ethernet switches. The traffic is described with flows and each flow is characterized by its source node, its destination node, its route and parameters in the generalized multiframe model. Output queues on Ethernet switches are scheduled by static-priority scheduling and tasks executing on the processor in an Ethernet switch are scheduled by stride scheduling. We present schedulability analysis for this setting.

A MOSFET-only wideband LNA exploiting thermal noise canceling and gain optimization

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

A Gß protein and the TupA Co-Regulator bind to protein kinase A Tpk2 to act as antagonistic molecular switches of fungal morphological changes

A Gß protein and the TupA Co-Regulator Bind to Protein Kinase A Tpk2 to Act as Antagonistic Molecular Switches of Fungal Morphological Changes

Design, modeling and fabrication of radio-frequency microelectromechanical switches and coplanar filters

Magdeburg, Univ., Fak. für Elektrotechnik und Informationstechnik, Diss., 2010

The evolutionary host switches of Polychromophilus: a multi-gene phylogeny of the bat malaria genus suggests a second invasion of mammals by a haemosporidian parasite.

BACKGROUND: The majority of Haemosporida species infect birds or reptiles, but many important genera, including Plasmodium, infect mammals. Dipteran vectors shared by avian, reptilian and mammalian Haemosporida, suggest multiple invasions of Mammalia during haemosporidian evolution; yet, phylogenetic analyses have detected only a single invasion event. Until now, several important mammal-infecting genera have been absent in these analyses. This study focuses on the evolutionary origin of Polychromophilus, a unique malaria genus that only infects bats (Microchiroptera) and is transmitted by bat flies (Nycteribiidae). METHODS: Two species of Polychromophilus were obtained from wild bats caught in Switzerland. These were molecularly characterized using four genes (asl, clpc, coI, cytb) from the three different genomes (nucleus, apicoplast, mitochondrion). These data were then combined with data of 60 taxa of Haemosporida available in GenBank. Bayesian inference, maximum likelihood and a range of rooting methods were used to test specific hypotheses concerning the phylogenetic relationships between Polychromophilus and the other haemosporidian genera. RESULTS: The Polychromophilus melanipherus and Polychromophilus murinus samples show genetically distinct patterns and group according to species. The Bayesian tree topology suggests that the monophyletic clade of Polychromophilus falls within the avian/saurian clade of Plasmodium and directed hypothesis testing confirms the Plasmodium origin. CONCLUSION: Polychromophilus' ancestor was most likely a bird- or reptile-infecting Plasmodium before it switched to bats. The invasion of mammals as hosts has, therefore, not been a unique event in the evolutionary history of Haemosporida, despite the suspected costs of adapting to a new host. This was, moreover, accompanied by a switch in dipteran host.

Suurnopeushilaohjain IGB-transistoreille

Hilalta ohjattavien tehokytkimien, kuten IGBT tai MOSFET, ohjaaminen toteutetaan ohjausjännitettä muuttamalla. Hilaohjaimen tehtävä on ladata tehokytkimen hilakapasitanssia ohjattuun jännitteeseen. Hilaohjaimen siirtämän varauksen suuruuteen vaikuttaa hilakapasitanssin todellinen suuruus ja käytettävä ohjausjännite. Hilaohjaimen virrankäsittelykyky määrittää hilaohjaimen nopeuden siinä mielessä, että ohjattavan komponentin hilavaraus tulisi pystyä lataamaan ja purkamaan tietyssä suhteessa kytkentätaajuuteen. Kytkentätaajuuksien kasvaessa myös hilaohjaimen virrankäsittelykyky sekä hilaohjaimen teho joutuvat uudelleen arvioitaviksi. Työssä perehdytään IGBT:n toimintaan ja hilaohjainratkaisuihin suurilla kytkentätaajuuksilla. Työssä ontutkittu mahdollisuutta rakentaa IGBT:n hilaohjain jo markkinoilla olevista MOSFET:ien hilaohjaimista. Suurnopeushilaohjaimesta suunnitellaanja rakennetaan prototyyppi. Prototyypin suoriutumista tehtävistään tarkastellaan tekemällä mittauksia. Lopuksi arvioidaan asioita joiden tulee muuttua matkalla kohti megahertsien kytkentätaajuuksia.

Thermal modelling of semiconductor switches in three-level Neutral Point Clamped Medium Voltage DTC-inverter

The aim of this thesis is to investigate the thermal loading of medium voltage three-level NPC inverter’s semiconductor IGCT switches in different operation points. The objective is to reach both a fairly accurate off-line simulation program and also so simple a simulation model that its implementation into an embedded system could be reasonable in practice and a real time use should become feasible. Active loading limitation of the inverter can be realized with a thermal model which is practical in a real time use. Determining of the component heating has been divided into two parts; defining of component losses and establishing the structure of a thermal network. Basics of both parts are clarified. The simulation environment is Matlab-Simulink. Two different models are constructed – a more accurate one and a simplified one. Potential simplifications are clarified with the help of the first one. Simplifications are included in the latter model and the functionalities of both models are compared. When increasing the calculation time step a decreased number of considered components and time constants of the thermal network can be used in the simplified model. Heating of a switching component is dependent on its topological position and inverter’s operation point. The output frequency of the converter defines mainly which one of the switching components is – because of its losses and heating – the performance limiting component of the converter. Comparison of results given by different thermal models demonstrates that with larger time steps, describing of fast occurring switching losses becomes difficult. Generally articles and papers dealing with this subject are written for two-level inverters. Also inverters which apply direct torque control (DTC) are investigated rarely from the heating point of view. Hence, this thesis completes the former material.