Theory and practice of automotive modal lock-in – an Indonesian case

This thesis examines the question why the automotive mode and the large technological system it creates, continues to dominate urban transport systems despite the availability of more cost-efficient alternatives. A number of theoretical insights are developed into the way these losses evolve from path dependent growth, and lead to market failure and lock-in. The important role of asymmetries of influence is highlighted. A survey of commuters in Jakarta Indonesia is used to provide a measure of transport modal lock-in (TML) in a developing country conurbation. A discrete choice experiment is used to provide evidence for the thesis central hypothesis that in such conurbations there is a high level of commuter awareness of the negative externalities generated by TML which can produce a strong level of support for its reversal. Why TML nevertheless remains a strong and durable feature of the transport system is examined with reference to the role of asymmetries of influence.

Automotive modal lock-in: The role of path dependence and large socio-economic regimes in market failure

This paper addresses less recognised factors which influence the diffusion of a particular technology. While an innovation’s attributes and performance are paramount, many fail because of external factors which favour an alternative. This paper, with theoretic input from diffusion, lock-in and path-dependency, presents a qualitative study of external factors that influenced the evolution of transportation in USA. This historical account reveals how one technology and its emergent systems become dominant while other choices are overridden by socio-political, economic and technological interests which include not just the manufacturing and service industries associated with the automobile but also government and market stakeholders. Termed here as a large socio-economic regime (LSER),its power in ensuring lock-in and continued path-dependency is shown to pass through three stages, weakening eventually as awareness improves. The study extends to transport trends in China, Korea, Indonesia and Malaysia and they all show the dominant role of an LSER. As transportation policy is increasingly accountable to address both demand and environmental concerns and innovators search for solutions, this paper presents important knowledge for innovators, marketers and policy makers for commercial and societal reasons, especially when negative externalities associated with an incumbent transportation technology may lead to market failure.

An Approximate Method For Calculation Of Fluid Force And Response Of A Circular Cylinder At Lock-In

In this paper, equations calculating lift force of a rigid circular cyclinder at lock-in uniform flow are deduced in detail. Besides, equations calculating the lift force on a long flexible circular cyclinder at lock-in are deduced based on mode analysis of a multi-degree freedom system. The simplified forms of these equations are also given. Furthermore, an approximate method to predict the forces and response of rigid circular cyclinders and long flexible circular cyclinders at lock-in is introduced in the case of low mass-damping ratio. A method to eliminate one deficiency of these equations is introduced. Comparison with experimental results show the effectiveness of this approximate method.

High-precision digital lock-in measurements of critical current and AC loss in HTS 2G-Tapes

Application of High Temperature Superconducting (HTS) has been increasingly popular since the new superconducting materials were discovered. This paper presents a new high-precision digital lock-in measurement technique which is used for measuring critical current and AC loss of the 2nd Generation HTS tape. Using a lock-in amplifier and nano-voltage meter, we can resolve signals at nano-volt level, while using a specially designed compensation coil we can cancel out inductive by adjusting the coil inductance. Furthermore, a finer correction for the inductive component can be achieved by adjusting the reference phase of the lock-in amplifier. The critical current and AC loss measurement algorithms and hardware layout are described and analyzed, and results for both numerical and experimental data under varieties of frequencies are presented. © 2008 SICE.

Lock-in and quasiperiodicity in a forced hydrodynamically self-excited jet

The ability of hydrodynamically self-excited jets to lock into strong external forcing is well known. Their dynamics before lock-in and the specific bifurcations through which they lock in, however, are less well known. In this experimental study, we acoustically force a low-density jet around its natural global frequency. We examine its response leading up to lock-in and compare this to that of a forced van der Pol oscillator. We find that, when forced at increasing amplitudes, the jet undergoes a sequence of two nonlinear transitions: (i) from periodicity to T{double-struck}2 quasiperiodicity via a torus-birth bifurcation; and then (ii) from T{double-struck}2 quasiperiodicity to 1:1 lock-in via either a saddle-node bifurcation with frequency pulling, if the forcing and natural frequencies are close together, or a torus-death bifurcation without frequency pulling, but with a gradual suppression of the natural mode, if the two frequencies are far apart. We also find that the jet locks in most readily when forced close to its natural frequency, but that the details contain two asymmetries: the jet (i) locks in more readily and (ii) oscillates more strongly when it is forced below its natural frequency than when it is forced above it. Except for the second asymmetry, all of these transitions, bifurcations and dynamics are accurately reproduced by the forced van der Pol oscillator. This shows that this complex (infinite-dimensional) forced self-excited jet can be modelled reasonably well as a simple (three-dimensional) forced self-excited oscillator. This result adds to the growing evidence that open self-excited flows behave essentially like low-dimensional nonlinear dynamical systems. It also strengthens the universality of such flows, raising the possibility that more of them, including some industrially relevant flames, can be similarly modelled. © 2013 Cambridge University Press.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer

This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small initial frequency error and greatly reduces the lock-in time. It can automatically compensate preset frequency variation with process and temperature. A 2.4GHz synthesizer with 1MHz reference input was implemented in 0.35 mu m CMOS process. The chip core area is 0.4mm(2). Output frequency of VCO ranges from 2390 to 2600MHz. The measured results show that the typical lock-in time is 3 mu s. The phase noise is -112dBc/Hz at 600KHz offset from center frequency. The test chip consumes current of 22mA that includes the consumption of the I/O buffers.