A 2kW interleaved ZCS-FM boost rectifier digitally controlled by FPGA device

This paper presents a 2kW single-phase high power factor boost rectifier with four cells in interleave connection, operating in critical conduction mode, and employing a soft-switching technique, controlled by Field Programmable Gate Array (FPGA). The soft-switching technique Is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-voltage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related 'to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the Interleaving technique, the rectifer's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) In the input current, in compliance with the TEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for four interleaved cells, and a closed-loop to provide the output voltage regulation, like as a pre-regulator rectifier. Experimental results are presented for a 2kW implemented prototype with four interleaved cells, 400V nominal output voltage and 220V(rms) nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device.

A phase-shifting control for variable frequency multi-cells interleaved boost pre-regulator based on FPGA device

In this paper were investigated phase-shift control strategies applied to a four cells interleaved high input-power-factor pre-regulator boost rectifier, operating in critical conduction mode, using a non-dissipative commutation cells and frequency modulation. The digital control has been developed using a hardware description language (VHDL) and implemented using the XC2S200E-SpartanII-E/Xilinx FPGA, performing a true critical conduction operation mode for a generic number of interleaved cells. Experimental results are presented, in order to verify the feasibility and performance of the proposed digital control, through the use of a Xilinx FPGA device.

An AC voltage regulator with high-power-factor, and control using a FPGA device

This paper presents the analysis, design, simulation, and experimental results for a high frequency high Power-Factor (PF) AC (Alternate Current) voltage regulator, using a Sepic converter as power stage. The control technique employed to impose a sinusoidal input current waveform, with low Total Harmonic Distortion (THD), is the sinusoidal variable hysteresis control. The control technique was implemented in a FPGA (Field Programmable Gate Array) device, using a Hardware Description Language (VHDL). Through the use of the proposed control technique, the AC voltage regulator performs active power-factor correction, and low THD in the input current, for linear and non-linear loads, satisfying the requirements of the EEC61000-3-2 standards. Experimental results from an example prototype, designed for 300W of nominal output power, 50kHz (switching frequency), and 127Vrms of nominal input and output voltages, are presented in order to validate the proposed AC regulator. © 2005 IEEE.

Hybrid three-phase HPF rectifier with programmable input current THD, using FPGA device and VHDL language

In this paper is proposed and analyzed a digital hysteresis modulation using a FPGA (Field Programmable Gate Array) device and VHDL (Hardware Description Language), applied at a hybrid three-phase rectifier with almost unitary input power factor, composed by parallel SEPIC controlled single-phase rectifiers connected to each leg of a standard 6-pulses uncontrolled diode rectifier. The digital control allows a programmable THD (Total Harmonic Distortion) at the input currents, and it makes possible that the power rating of the switching-mode converters, connected in parallel, can be a small fraction of the total average output power, in order to obtain a compact converter, reduced input current THD and almost unitary input power factor. Finally, the proposed digital control, using a FPGA device and VHDL, offers an important flexibility for the associated control technique, in order to obtain a programmable PFC (Power Factor Correction) hybrid three-phase rectifier, in agreement with the international standards (IEC, and IEEE), which impose limits for the THD of the AC (Alternate Current) line input currents. The proposed strategy is verified by experiments. © 2008 IEEE.

Verification and FPGA circuits of a block-2 fast path-based predictor

This paper formally derives a new path-based neural branch prediction algorithm (FPP) into blocks of size two for a lower hardware solution while maintaining similar input-output characteristic to the algorithm. The blocked solution, here referred to as B2P algorithm, is obtained using graph theory and retiming methods. Verification approaches were exercised to show that prediction performances obtained from the FPP and B2P algorithms differ within one mis-prediction per thousand instructions using a known framework for branch prediction evaluation. For a chosen FPGA device, circuits generated from the B2P algorithm showed average area savings of over 25% against circuits for the FPP algorithm with similar time performances thus making the proposed blocked predictor superior from a practical viewpoint.

Desenvolvimento de uma arquitetura em hardware prototipada em FPGA para aplicações genéricas utilizando redes neurais artificiais embarcadas

This work proposes hardware architecture, VHDL described, developed to embedded Artificial Neural Network (ANN), Multilayer Perceptron (MLP). The present work idealizes that, in this architecture, ANN applications could easily embed several different topologies of MLP network industrial field. The MLP topology in which the architecture can be configured is defined by a simple and specifically data input (instructions) that determines the layers and Perceptron quantity of the network. In order to set several MLP topologies, many components (datapath) and a controller were developed to execute these instructions. Thus, an user defines a group of previously known instructions which determine ANN characteristics. The system will guarantee the MLP execution through the neural processors (Perceptrons), the components of datapath and the controller that were developed. In other way, the biases and the weights must be static, the ANN that will be embedded must had been trained previously, in off-line way. The knowledge of system internal characteristics and the VHDL language by the user are not needed. The reconfigurable FPGA device was used to implement, simulate and test all the system, allowing application in several real daily problems

A multi-cell variable frequency interleaved ZCS boost rectifier digitally controlled by FPGA

This paper presents a multi-cell single-phase high power factor boost rectifier in interleave connection, operating in critical conduction mode, employing a soft-switching technique, and controlled by Field Programmable Gate Array (FPGA). The soft-switching technique is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-vohage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the interleaving technique, the rectifier's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the IEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for all interleaved cells, and a closed-loop to provide the output voltage regulation, like as a preregulator rectifier. Experimental results are presented for a implemented prototype with two and with four interleaved cells, 400V nominal output voltage and 220V(rms) nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device.

Controle digital através de dispositivo FPGA aplicado a um retificador trifásico híbrido operando com modulação por histerese variável

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Pré-regulador retificador entrelaçado (Interleaved) ZCS-FM boost, com controle digital através de dispositivo FPGA e linguagem VHDL

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Development of Efficient FPGA-Based Multi-Channel Phase Meters for IR-Interferometers

Infrared (IR) interferometry is a method for measuring the line-electron density of fusion plasmas. The significant performance achieved by FPGAs in solving digital signal processing tasks advocates the use of this type of technology in two-color IR interferometers of modern stellarators, such as the TJ-II (Madrid, Spain) and the future W7-X (Greifswald, Germany). In this work the implementation of a line-average electron density measuring system in an FPGA device is described. Several optimizations for multichannel systems are detailed and test results from the TJ-II as well as from a W7-X prototype are presented.

Simulating spin systems on IANUS, an FPGA-based computer

We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is comparable to O(100) carefully programmed high-end PCs: it turns out to be even better for some selected spin models. We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system.

Modelo comportamental do capacitor ferroelétrico como unidade básica de neurônios artificiais e sua implementação em FPGA

This work proposes the use of the behavioral model of the hysteresis loop of the ferroelectrics capacitor as a new alternative to the usually costly techniques in the computation of nonlinear functions in artificial neurons implemented on reconfigurable hardware platform, in this case, a FPGA device. Initially the proposal has been validated by the implementation of the boolean logic through the digital models of two artificial neurons: the Perceptron and a variation of the model Integrate and Fire Spiking Neuron, both using the model also digital of the hysteresis loop of the ferroelectric capacitor as it’s basic nonlinear unit for the calculations of the neurons outputs. Finally, it has been used the analog model of the ferroelectric capacitor with the goal of verifying it’s effectiveness and possibly the reduction of the number of necessary logic elements in the case of implementing the artificial neurons on integrated circuit. The implementations has been carried out by Simulink models and the synthesizing has been done through the DSP Builder software from Altera Corporation.

Multiprocessor platform using LEON3 processor

The recent advances in embedded systems world, lead us to more complex systems with application specific blocks (IP cores), the System on Chip (SoC) devices. A good example of these complex devices can be encountered in the cell phones that can have image processing cores, communication cores, memory card cores, and others. The need of augmenting systems’ processing performance with lowest power, leads to a concept of Multiprocessor System on Chip (MSoC) in which the execution of multiple tasks can be distributed along various processors. This thesis intends to address the creation of a synthesizable multiprocessing system to be placed in a FPGA device, providing a good flexibility to tailor the system to a specific application. To deliver a multiprocessing system, will be used the synthesisable 32-bit SPARC V8 compliant, LEON3 processor.

Projeto e implementação de um pré-regulador de fator de potência com controlo digital

Hoje em dia as fontes de alimentação possuem correção do fator de potência, devido às diversas normas regulamentares existentes, que introduziram grandes restrições no que respeita à distorção harmónica (THD) e fator de potência (FP). Este trabalho trata da análise, desenvolvimento e implementação de um Pré-Regulador de fator de potência com controlo digital. O controlo digital de conversores com recurso a processamento digital de sinal tem vindo a ser ao longo dos últimos anos, objeto de investigação e desenvolvimento, estando constantemente a surgirem modificações nas topologias existentes. Esta dissertação tem como objetivo estudar e implementar um Pré-Regulador Retificador Boost e o respetivo controlo digital. O controlo do conversor é feito através da técnica dos valores médios instantâneos da corrente de entrada, desenvolvido através da linguagem de descrição de hardware VHDL (VHSIC HDL – Very High Speed Integrated Circuit Hardware Description Language) e implementado num dispositivo FPGA (Field Programmable Gate Array) Spartan-3E. Neste trabalho são apresentadas análises matemáticas, para a obtenção das funções de transferência pertinentes ao projeto dos controladores. Para efetuar este controlo é necessário adquirir os sinais da corrente de entrada, tensão de entrada e tensão de saída. O sinal resultante do módulo de controlo é um sinal de PWM com valor de fator de ciclo variável ao longo do tempo. O projeto é simulado e validado através da plataforma MatLab/Simulink e PSIM, onde são apresentados resultados para o regime permanente e para transitórios da carga e da tensão de alimentação. Finalmente, o Pré-Regulador Retificador Boost controlado de forma digital é implementado em laboratório. Os resultados experimentais são apresentados para validar a metodologia e o projeto desenvolvidos.

Study of Control Methods of a High-Frequency Cycloconverter for Domestic Induction Heating Appliances

A high-frequency cyclonverter acts as a direct ac-to-ac power converter circuit that does not require a diode bidge rectifier. Bridgeless topology makes it possible to remove forward voltage drop losses that are present in a diode bridge. In addition, the on-state losses can be reduced to 1.5 times the on-state resistance of switches in half-bridge operation of the cycloconverter. A high-frequency cycloconverter is reviewed and the charging effect of the dc-capacitors in ``back-to-back'' or synchronous mode operation operation is analyzed. In addition, a control method is introduced for regulating dc-voltage of the ac-side capacitors in synchronous operation mode. The controller regulates the dc-capacitors and prevents switches from reaching overvoltage level. This can be accomplished by variating phase-shift between the upper and the lower gate signals. By adding phase-shift between the gate signal pairs, the charge stored in the energy storage capacitors can be discharged through the resonant load and substantially, the output resonant current amplitude can be improved. The above goals are analyzed and illustrated with simulation. Theory is supported with practical measurements where the proposed control method is implemented in an FPGA device and tested with a high-frequency cycloconverter using super-junction power MOSFETs as switching devices.