A low-power silicon-on-insulator PWM discriminator for biomedical applications

A CMOS/SOI circuit to decode PWM signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a double-integration concept and does not require dc filtering. Nonoverlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 mu m single-metal SOI fabrication process and has an effective area of 2mm(2) Typically, the measured resolution of encoding parameter a was better than 10% at 6MHz and V-DD=3.3V. Stand-by consumption is around 340 mu W. Pulses with frequencies up to 15MHz and alpha = 10% can be discriminated for V-DD spanning from 2.3V to 3.3V. Such an excellent immunity to V-DD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.

Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects

The progresses of electron devices integration have proceeded for more than 40 years following the well–known Moore’s law, which states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face them. In order to overcome the limitations related to conventional structures, the researchers community is preparing different solutions, that need to be assessed. Possible solutions currently under scrutiny are represented by: • devices incorporating materials with properties different from those of silicon, for the channel and the source/drain regions; • new architectures as Silicon–On–Insulator (SOI) transistors: the body thickness of Ultra-Thin-Body SOI devices is a new design parameter, and it permits to keep under control Short–Channel–Effects without adopting high doping level in the channel. Among the solutions proposed in order to overcome the difficulties related to scaling, we can highlight heterojunctions at the channel edge, obtained by adopting for the source/drain regions materials with band–gap different from that of the channel material. This solution allows to increase the injection velocity of the particles travelling from the source into the channel, and therefore increase the performance of the transistor in terms of provided drain current. The first part of this thesis work addresses the use of heterojunctions in SOI transistors: chapter 3 outlines the basics of the heterojunctions theory and the adoption of such approach in older technologies as the heterojunction–bipolar–transistors; moreover the modifications introduced in the Monte Carlo code in order to simulate conduction band discontinuities are described, and the simulations performed on unidimensional simplified structures in order to validate them as well. Chapter 4 presents the results obtained from the Monte Carlo simulations performed on double–gate SOI transistors featuring conduction band offsets between the source and drain regions and the channel. In particular, attention has been focused on the drain current and to internal quantities as inversion charge, potential energy and carrier velocities. Both graded and abrupt discontinuities have been considered. The scaling of devices dimensions and the adoption of innovative architectures have consequences on the power dissipation as well. In SOI technologies the channel is thermally insulated from the underlying substrate by a SiO2 buried–oxide layer; this SiO2 layer features a thermal conductivity that is two orders of magnitude lower than the silicon one, and it impedes the dissipation of the heat generated in the active region. Moreover, the thermal conductivity of thin semiconductor films is much lower than that of silicon bulk, due to phonon confinement and boundary scattering. All these aspects cause severe self–heating effects, that detrimentally impact the carrier mobility and therefore the saturation drive current for high–performance transistors; as a consequence, thermal device design is becoming a fundamental part of integrated circuit engineering. The second part of this thesis discusses the problem of self–heating in SOI transistors. Chapter 5 describes the causes of heat generation and dissipation in SOI devices, and it provides a brief overview on the methods that have been proposed in order to model these phenomena. In order to understand how this problem impacts the performance of different SOI architectures, three–dimensional electro–thermal simulations have been applied to the analysis of SHE in planar single and double–gate SOI transistors as well as FinFET, featuring the same isothermal electrical characteristics. In chapter 6 the same simulation approach is extensively employed to study the impact of SHE on the performance of a FinFET representative of the high–performance transistor of the 45 nm technology node. Its effects on the ON–current, the maximum temperatures reached inside the device and the thermal resistance associated to the device itself, as well as the dependence of SHE on the main geometrical parameters have been analyzed. Furthermore, the consequences on self–heating of technological solutions such as raised S/D extensions regions or reduction of fin height are explored as well. Finally, conclusions are drawn in chapter 7.

Characterization of integrated Bragg gratings in silicon-on-insulator

Silicon-on-insulator (SOI) is rapidly emerging as a very promising material platform for integrated photonics. As it combines the potential for optoelectronic integration with the low-cost and large volume manufacturing capabilities and they are already accumulate a huge amount of applications in areas like sensing, quantum optics, optical telecommunications and metrology. One of the main limitations of current technology is that waveguide propagation losses are still much higher than in standard glass-based platform because of many reasons such as bends, surface roughness and the very strong optical confinement provided by SOI. Such high loss prevents the fabrication of efficient optical resonators and complex devices severely limiting the current potential of the SOI platform. The project in the first part deals with the simple waveguides loss problem and trying to link that with the polarization problem and the loss based on Fabry-Perot Technique. The second part of the thesis deals with the Bragg Grating characterization from again the point of view of the polarization effect which leads to a better stop-band use filters. To a better comprehension a brief review on the basics of the SOI and the integrated Bragg grating ends up with the fabrication techniques and some of its applications will be presented in both parts, until the end of both the third and the fourth chapters to some results which hopefully make its precedent explanations easier to deal with.

Study of Periodic and Quasi-Periodic Structures in Silicon-on-Insulator

In this thesis, a numerical design approach has been proposed and developed based on the transmission matrix method in order to characterize periodic and quasi-periodic photonic structures in silicon-on-insulator. The approach and its performance have been extensively tested with specific structures in 2D and its validity has been verified in 3D.

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-K dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. (C) 2008 Elsevier Ltd. All rights reserved.

Raman scattering and photoluminescence analysis of silicon on insulator structures obtained by single and multiple oxygen implants

An analysis of silicon on insulator structures obtained by single and multiple implants by means of Raman scattering and photoluminescence spectroscopy is reported. The Raman spectra obtained with different excitation powers and wavelengths indicate the presence of a tensile strain in the top silicon layer of the structures. The comparison between the spectra measured in both kinds of samples points out the existence in the multiple implant material of a lower strain for a penetration depth about 300 nm and a higher strain for higher penetration depths. These results have been correlated with transmission electron microscopy observations, which have allowed to associate the higher strain to the presence of SiO2 precipitates in the top silicon layer, close to the buried oxide. The found lower strain is in agreement with the better quality expected for this material, which is corroborated by the photoluminescence data.

Raman microstructural analysis of silicon-on-insulator formed by high dose oxygen ion implantation: As-implanted structures

A microstructural analysis of silicon-on-insulator samples obtained by high dose oxygen ion implantation was performed by Raman scattering. The samples analyzed were obtained under different conditions thus leading to different concentrations of defects in the top Si layer. The samples were implanted with the surface covered with SiO2 capping layers of different thicknesses. The spectra measured from the as-implanted samples were fitted to a correlation length model taking into account the possible presence of stress effects in the spectra. This allowed quantification of both disorder effects, which are determined by structural defects, and residual stress in the top Si layer before annealing. These data were correlated to the density of dislocations remaining in the layer after annealing. The analysis performed corroborates the existence of two mechanisms that generate defects in the top Si layer that are related to surface conditions during implantation and the proximity of the top Si/buried oxide layer interface to the surface before annealing.

Characteristics of small-signal capacitances of silicon-on-sapphire MOSFETs

The measured inter-electrode capacitances of silicon-on-sapphire (SOS) MOSFETs are presented and compared with simulation results. It is shown that the variations of capacitances with DC bias differ from those of bulk MOSFETs due to change in body potential variation of the SOS device resulting from electron-hole pair generation through impact ionisation.

Neutron diffraction analysis on FINEMET alloys

Neutron diffraction has been used to study in situ the nanocrystallization process of Fe73.5Cu1Nb3Si22.5-xBx (x = 5, 9, and 12) amorphous alloys. Nanocrystallization results in a decrease of both the silicon content and the grain size of the Fe(Si) phase with increasing value of x. By comparing the radial distribution function peak areas with those predicted for ideal bcc and DO3 structure, it can be concluded that the ordering in DO3 Fe(Si) crystals increases with the silicon content.

Strained Silicon on Silicon by Wafer Bonding and Layer Transfer from Relaxed SiGe Buffer

We report the creation of strained silicon on silicon (SSOS) substrate technology. The method uses a relaxed SiGe buffer as a template for inducing tensile strain in a Si layer, which is then bonded to another Si handle wafer. The original Si wafer and the relaxed SiGe buffer are subsequently removed, thereby transferring a strained-Si layer directly to Si substrate without intermediate SiGe or oxide layers. Complete removal of Ge from the structure was confirmed by cross-sectional transmission electron microscopy as well as secondary ion mass spectrometry. A plan-view transmission electron microscopy study of the strained-Si/Si interface reveals that the lattice-mismatch between the layers is accommodated by an orthogonal array of edge dislocations. This misfit dislocation array, which forms upon bonding, is geometrically necessary and has an average spacing of approximately 40nm, in excellent agreement with established dislocation theory. To our knowledge, this is the first study of a chemically homogeneous, yet lattice-mismatched, interface.

Taking Root in the Silicon Forest: High-technology Firms as Surrogate Universities in Portland, Oregon

Most case studies of successful high-technology industry regions highlight the role of research universities in fostering regional economic development. The Portland, Oregon, region managed to root a thriving high-tech industry in the absence of this critical factor. In this article, I present a case study of the evolution of Portland's high-tech industry and propose that high-tech firms can act as surrogate universities that attract and develop labor, create knowledge, and function as incubators for startups. I conclude that planners working to develop high-tech industries in regions without major research universities should attract R&D-intensive firms, maintain information on key busineses and entrepreneurial ventures, support an innovation milieu, and set realistic goals.

Identification of intermediate debonding damage in FRP-plated RC beams based on multi-objective particle swarm optimization without updated baseline model

Fiber reinforced polymer composites (FRP) have found widespread usage in the repair and strengthening of concrete structures. FRP composites exhibit high strength-to-weight ratio, corrosion resistance, and are convenient to use in repair applications. Externally bonded FRP flexural strengthening of concrete beams is the most extended application of this technique. A common cause of failure in such members is associated with intermediate crack-induced debonding (IC debonding) of the FRP substrate from the concrete in an abrupt manner. Continuous monitoring of the concrete?FRP interface is essential to pre- vent IC debonding. Objective condition assessment and performance evaluation are challenging activities since they require some type of monitoring to track the response over a period of time. In this paper, a multi-objective model updating method integrated in the context of structural health monitoring is demonstrated as promising technology for the safety and reliability of this kind of strengthening technique. The proposed method, solved by a multi-objective extension of the particle swarm optimization method, is based on strain measurements under controlled loading. The use of permanently installed fiber Bragg grating (FBG) sensors embedded into the FRP-concrete interface or bonded onto the FRP strip together with the proposed methodology results in an automated method able to operate in an unsupervised mode.

Design of equalized ROADMs devices with flexible bandwidth based on LCoS technology

This paper describes the theory, design, applications and performance of a new Reconfigurable Add-drop Multiplexer (ROADM) with flexible bandwidth allocation. The device can address several wavelengths at the input to four output fibers, according to the holograms stored in a SLM (Spatial Light Modulator), where all the outputs are equalized in power. All combinations of the input wavelengths are possible at the different output fibers. Each fiber has assigned all the signals with the same bandwidth; the possible bandwidths are 12.5GHz, 25GHz, 50GHz and 100GHz, according to ITU-T 694.1 Recommendation. It is possible to route several signals with different bandwidth in real time thanks to Liquid Crystal over Silicon (LCoS) technology.

Trapezoidal cross-sectional influence on FinFET threshold voltage and corner effects

Fin field effect transistors (FinFETS) are silicon-on-insulator (SOI) transistors with three-dimensional structures. As a result of some fabrication-process limitations (as nonideal anisotropic overetch) some FinFETs have inclined surfaces, which results in trapezoidal cross sections instead of rectangular sections, as expected. This geometric alteration results in some device issues, like carrier profile, threshold voltage, and corner effects. This work analyzes these consequences based on three-dimensional numeric simulation of several dual-gate and triple-gate FinFETs. The simulation results show that the threshold voltage depends on the sidewall inclination angle and that this dependence varies according to the body doping level. The corner effects also depend on the inclination angle and doping level. (C) 2008 The Electrochemical Society.