A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

Phase noise and spur reduction in an array of direct digital synthesizers

Many applications, including communications, test and measurement, and radar, require the generation of signals with a high degree of spectral purity. One method for producing tunable, low-noise source signals is to combine the outputs of multiple direct digital synthesizers (DDSs) arranged in a parallel configuration. In such an approach, if all noise is uncorrelated across channels, the noise will decrease relative to the combined signal power, resulting in a reduction of sideband noise and an increase in SNR. However, in any real array, the broadband noise and spurious components will be correlated to some degree, limiting the gains achieved by parallelization. This thesis examines the potential performance benefits that may arise from using an array of DDSs, with a focus on several types of common DDS errors, including phase noise, phase truncation spurs, quantization noise spurs, and quantizer nonlinearity spurs. Measurements to determine the level of correlation among DDS channels were made on a custom 14-channel DDS testbed. The investigation of the phase noise of a DDS array indicates that the contribution to the phase noise from the DACs can be decreased to a desired level by using a large enough number of channels. In such a system, the phase noise qualities of the source clock and the system cost and complexity will be the main limitations on the phase noise of the DDS array. The study of phase truncation spurs suggests that, at least in our system, the phase truncation spurs are uncorrelated, contrary to the theoretical prediction. We believe this decorrelation is due to the existence of an unidentified mechanism in our DDS array that is unaccounted for in our current operational DDS model. This mechanism, likely due to some timing element in the FPGA, causes some randomness in the relative phases of the truncation spurs from channel to channel each time the DDS array is powered up. This randomness decorrelates the phase truncation spurs, opening the potential for SFDR gain from using a DDS array. The analysis of the correlation of quantization noise spurs in an array of DDSs shows that the total quantization noise power of each DDS channel is uncorrelated for nearly all values of DAC output bits. This suggests that a near N gain in SQNR is possible for an N-channel array of DDSs. This gain will be most apparent for low-bit DACs in which quantization noise is notably higher than the thermal noise contribution. Lastly, the measurements of the correlation of quantizer nonlinearity spurs demonstrate that the second and third harmonics are highly correlated across channels for all frequencies tested. This means that there is no benefit to using an array of DDSs for the problems of in-band quantizer nonlinearities. As a result, alternate methods of harmonic spur management must be employed.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS.The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm~2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

Additive manufacturing technologies : 3D printing, rapid prototyping, and direct digital manufacturing

This book covers in detail the various aspects of joining materials to form parts. A conceptual overview of rapid prototyping and layered manufacturing is given, beginning with the fundamentals so that readers can get up to speed quickly. Unusual and emerging applications such as micro-scale manufacturing, medical applications, aerospace, and rapid manufacturing are also discussed. This book provides a comprehensive overview of rapid prototyping technologies as well as support technologies such as software systems, vacuum casting, investment casting, plating, infiltration and other systems. This book also: Reflects recent developments and trends and adheres to the ASTM, SI, and other standards Includes chapters on automotive technology, aerospace technology and low-cost AM technologies Provides a broad range of technical questions to ensure comprehensive understanding of the concepts covered.

Primary tooth length determination in direct digital radiography: An in vivo study

Purpose: the purpose of this in vivo study was to compare the accuracy of primary incisor length determined by direct digital radiography (straight-line measurement and grid superimposition) and measurement of the actual tooth length. Methods. Twenty-two primary maxillary incisors that required extractions were selected from 3- to 5-year-old children. The teeth were radiographed with an intraoral sensor using the long cone technique and a sensor holder (30-cm focus-to-sensor distance). The exposure time was 03 seconds. Tooth length was estimated by using straight-line and grid measurements provided by the distance measurement feature of the Computed Dental Radiography digital dental imaging system. The actual tooth length was obtained by measuring the extracted tooth with G digital caliper. Data were analyzed statistically by Pearson's correlation coefficient and a paired t test. Results: There were statistically significant differences (P=.007) between the 2 measurement techniques and between the actual tooth lengths and grid measurements. There was no statistically significant difference (P=38) between straight-line measurements and actual tooth lengths, showing that the straight-line measurements were more accurate. Underestimation of the actual tooth length, however, occurred in 45% of the straight-line measurements and in 73% of the grid measurements. Conclusion: It is possible to determine primary tooth length in digital radiographs using onscreen measurements with 0 reasonable degree of accuracy.

Comparison of direct digital and conventional imaging with Ekta Speed Plus and INSIGHT films for the detection of approximal caries

Purpose: To evaluate the accuracy of approximal caries detection comparing enhanced and unenhanced Sidexis CCD-based digital image with Ektaspeed Plus and INSIGHT films. Methods: Fifty-two extracted premolars were imaged under identical standardized geometric and exposure conditions. Four observers, using five points confidence scale, rated 104 approximal surfaces for the presence or absence of carious lesions by means of four image modalities: (1) observer enhanced; (2) unenhanced Sidexis displays; (3) E speed films and (4) F speed film. Histologic sections served as validating criterion for the presence and depth of carious lesions. Diagnostic accuracy was measured as the area beneath the ROC curve. Results: Mean ROC (receiver operating characteristic) curve areas for approximal surfaces were 0.865 (E speed), 0.856 (F speed), 0.816 (unenhanced Sidexis) and 0.776 (observer enhanced). There were no significant differences between unenhanced digital Sidexis and films. Observer enhanced Sidexis images exhibited a statistically significant lower diagnostic accuracy than the film images for two of the observers.

[Head movements during simulated direct digital radiography]

The aim of this study was to simulate direct-digital cephalometric procedures and to record the head movements of probands. This study was prompted by the Committee for Insurance Matters of the Swiss National Invalidity Insurance which does not accept scanned digital cephalometric radiographs as a basis for its decisions. The reason for this is the required scanning time of several seconds during which even slight head movements can lead to kinetic blurring and landmark displacement. Incorrect angular measurements may result. By means of a Sirognathograph and a cephalostat of non-ferromagnetic material, the head movements of a total of 264 subjects were recorded in three dimensions, with a scanning time of up to 25 seconds. In a second series, the influence of a chin support to reduce head movements was also tested. The results of the first series of tests showed that, with an increasing scan time, movements became greater, mostly in the sagittal plane, and that maximum displacements could occur already at the start of the recording. With a scan time of 10 seconds the median movement amplitude in the vertical dimension was 2.14 mm. The second series of tests revealed a significant reduction in head movements in all dimensions owing to an additional stabilizing chin support. To minimize head movements, scanning times must be reduced and additional head stabilizing elements together with existing ones are necessary.

A new microcontrolled structural health monitoring system based on the electromechanical impedance principle

This article presents a new method to detect damage in structures based on the electromechanical impedance principle. The system follows the variations in the output voltage of piezoelectric transducers and does not compute the impedance itself. The proposed system is portable, autonomous, versatile, and could efficiently replace commercial instruments in different structural health monitoring applications. The identification of damage is performed by simply comparing the variations of root mean square voltage from response signals of piezoelectric transducers, such as lead zirconate titanate patches bonded to the structure, obtained for different frequencies of the excitation signal. The proposed system is not limited by the sampling rate of analog-to-digital converters, dispenses Fourier transform algorithms, and does not require a computer for processing, operating autonomously. A low-cost prototype based on microcontroller and digital synthesizer was built, and experiments were carried out on an aluminum structure and excellent results have been obtained. © The Author(s) 2012.