Design Space Exploration for MPSoC Architectures

Multiprocessor system-on-chip (MPSoC) designs utilize the available technology and communication architectures to meet the requirements of the upcoming applications. In MPSoC, the communication platform is both the key enabler, as well as the key differentiator for realizing efficient MPSoCs. It provides product differentiation to meet a diverse, multi-dimensional set of design constraints, including performance, power, energy, reconfigurability, scalability, cost, reliability and time-to-market. The communication resources of a single interconnection platform cannot be fully utilized by all kind of applications, such as the availability of higher communication bandwidth for computation but not data intensive applications is often unfeasible in the practical implementation. This thesis aims to perform the architecture-level design space exploration towards efficient and scalable resource utilization for MPSoC communication architecture. In order to meet the performance requirements within the design constraints, careful selection of MPSoC communication platform, resource aware partitioning and mapping of the application play important role. To enhance the utilization of communication resources, variety of techniques such as resource sharing, multicast to avoid re-transmission of identical data, and adaptive routing can be used. For implementation, these techniques should be customized according to the platform architecture. To address the resource utilization of MPSoC communication platforms, variety of architectures with different design parameters and performance levels, namely Segmented bus (SegBus), Network-on-Chip (NoC) and Three-Dimensional NoC (3D-NoC), are selected. Average packet latency and power consumption are the evaluation parameters for the proposed techniques. In conventional computing architectures, fault on a component makes the connected fault-free components inoperative. Resource sharing approach can utilize the fault-free components to retain the system performance by reducing the impact of faults. Design space exploration also guides to narrow down the selection of MPSoC architecture, which can meet the performance requirements with design constraints.

An Interpolative Analytical Cache Model with Application to Performance-Power Design Space Exploration

Caches are known to consume up to half of all system power in embedded processors. Co-optimizing performance and power of the cache subsystems is therefore an important step in the design of embedded systems, especially those employing application specific instruction processors. In this project, we propose an analytical cache model that succinctly captures the miss performance of an application over the entire cache parameter space. Unlike exhaustive trace driven simulation, our model requires that the program be simulated once so that a few key characteristics can be obtained. Using these application-dependent characteristics, the model can span the entire cache parameter space consisting of cache sizes, associativity and cache block sizes. In our unified model, we are able to cater for direct-mapped, set and fully associative instruction, data and unified caches. Validation against full trace-driven simulations shows that our model has a high degree of fidelity. Finally, we show how the model can be coupled with a power model for caches such that one can very quickly decide on pareto-optimal performance-power design points for rapid design space exploration.

System level design space exploration for MPSoC : methods, algorithms and new infrastructure

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Design state exploration applied to the development of a remote lab for projectile launch experiments

This paper describes the application of Design State Exploration techniques in the development of a remote lab for projectile motion experiments. The application was enabled by the existence of two independent teams: one composed of a series of internships that started first and another with two grantees that started a few months later. The paper presents evidence on how this approach provided gains in the development process conducted by the second team that benefited from design state exploration studies performed by the first team. This particular aspect is highlighted in relation to the work already presented in the 10th Remote Engineering and Virtual Instrumentation (REV) conference.

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.

Multithreading RTOS processor design

Tese de Doutoramento Plano Doutoral em Engenharia Eletrónica e de Computadores.

Le rôle de la rhétorique dans le projet en design : une exploration du concept d’argumentation de Perelman et Olbrechts-Tyteca

Les projets interdisciplinaires constituent rarement le terrain des études 
sur le processus de conception en design. Les théories générales du design, en tentant de définir ce qui est commun à toutes les disciplines du design, ont davantage étudié les cas typiques que les cas atypiques. Or, nous croyons qu’il existe dans les projets interdisciplinaires une négociation argumentative et une ouverture vers l’autre, propice à l’analyse du processus de conception en design. Pour réaliser l’étude de ce processus, la stratégie empruntée a été la «recherche-projet» qui propose une participation active sur le terrain. 
À l’intérieur de cette stratégie méthodologique, nous avons réalisé l’étude de cas d’un projet hybride, une signalétique identitaire destinée à marquer les écocentres montréalais et orienter leurs usagers. Comme plusieurs autres pratiques du design, la complexité des projets interdisciplinaires demande l’apport de plusieurs acteurs dans le processus. 
Ces personnes conçoivent le projet à travers des représentations visuelles et des échanges verbaux, nous avons choisi de faire porter notre étude principalement sur le second. Pour ce faire, nous avons choisi comme cadre théorique le Traité de l’argumentation de Chaïm Perelman et Lucie Olbrechts-Tyteca en nous intéressant plus spécifiquement aux concepts d’«accord» et d’«auditoire». Parce que le véhicule de l’action en design est la notion de «projet», l’Anthropologie du projet de Jean-Pierre Boutinet sera notre guide à travers cette conduite. L’objet de recherche de ce mémoire sera donc le processus de conception en design qui sera étudié à travers le regard de l’argumentation. L’argumentation s'est révélée la clé du problème que posent les jugements de valeur, commune à toutes les disciplines du design. Qu’est-ce qu’un «bon» projet réalisé? Est-il possible de répondre à cette question, sans tomber dans un cadre argumentatif, sans devoir révéler les arguments qui nous permettent de croire vraisemblable une telle proposition? C’est en mettant en lien la théorie du projet en design et la théorie de l’argumentation que nous avons éclairé la pratique du designer, sa relation à ses collègues et ultimement avec lui-même. L’argumentation s’est avérée un outil permettant la construction de la réalité dans le projet interdisciplinaire.

Space exploration.

Los seres humanos siempre han sentido curiosidad por el espacio y se han preguntado sobre que hay más allá de la Tierra, cómo se aprecia en algunas novelas de ciencia-ficción. Tras explicar el concepto de espacio, se repasa la historia de la exploración y la carrera espaciales, de los cohetes científicos y de sus primeros tripulantes. Por último, se hace un resumen de la preparación física de los astronautas, de las estaciones, satélites y sondas enviadas para la investigación espacial y de su tecnología; pero, también, se mencionan los peligros y desatres que la rodean.

Digital signal processing and digital system design using discrete cosine transform [student course]

The discrete cosine transform (DCT) is an important functional block for image processing applications. The implementation of a DCT has been viewed as a specialized research task. We apply a micro-architecture based methodology to the hardware implementation of an efficient DCT algorithm in a digital design course. Several circuit optimization and design space exploration techniques at the register-transfer and logic levels are introduced in class for generating the final design. The students not only learn how the algorithm can be implemented, but also receive insights about how other signal processing algorithms can be translated into a hardware implementation. Since signal processing has very broad applications, the study and implementation of an extensively used signal processing algorithm in a digital design course significantly enhances the learning experience in both digital signal processing and digital design areas for the students.

Fault tolerant embedded systems design by multi-objective optimization

The design of fault tolerant systems is gaining importance in large domains of embedded applications where design constrains are as important as reliability. New software techniques, based on selective application of redundancy, have shown remarkable fault coverage with reduced costs and overheads. However, the large number of different solutions provided by these techniques, and the costly process to assess their reliability, make the design space exploration a very difficult and time-consuming task. This paper proposes the integration of a multi-objective optimization tool with a software hardening environment to perform an automatic design space exploration in the search for the best trade-offs between reliability, cost, and performance. The first tool is commanded by a genetic algorithm which can simultaneously fulfill many design goals thanks to the use of the NSGA-II multi-objective algorithm. The second is a compiler-based infrastructure that automatically produces selective protected (hardened) versions of the software and generates accurate overhead reports and fault coverage estimations. The advantages of our proposal are illustrated by means of a complex and detailed case study involving a typical embedded application, the AES (Advanced Encryption Standard).

Telescopes and space exploration /

Mode of access: Internet.

Gas dynamics in space exploration.

Cover title.

Complex temporal patterns in molecular dynamics:a direct measure of the phase-space exploration by the trajectory at macroscopic time scales

Computer simulated trajectories of bulk water molecules form complex spatiotemporal structures at the picosecond time scale. This intrinsic complexity, which underlies the formation of molecular structures at longer time scales, has been quantified using a measure of statistical complexity. The method estimates the information contained in the molecular trajectory by detecting and quantifying temporal patterns present in the simulated data (velocity time series). Two types of temporal patterns are found. The first, defined by the short-time correlations corresponding to the velocity autocorrelation decay times (â‰0.1â€ps), remains asymptotically stable for time intervals longer than several tens of nanoseconds. The second is caused by previously unknown longer-time correlations (found at longer than the nanoseconds time scales) leading to a value of statistical complexity that slowly increases with time. A direct measure based on the notion of statistical complexity that describes how the trajectory explores the phase space and independent from the particular molecular signal used as the observed time series is introduced. © 2008 The American Physical Society.

Expanding the Design Space: Forging the Transition from 3D Printing to Additive Manufacturing

Thesis (Master's)--University of Washington, 2016-08