The Columbian calculator : being a practical and concise system of decimal arithmetic : adapted to the use of schools in the United States /

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The five orders of architecture : containing the most plain and simple rules for drawing and executing them in the purest style, for the use of workmen : exhibiting the most approved modes of applying each in practice, suitably to the climate of Great Britain ; including an historical description of Gothic architecture, illustrated with specimens selected from the most celebrated structures now existing, and numerous plans, elevations, sections, and details of various buildings executed by architects of great eminence : to which are added treatises on projection, perspective, fractions, decimal arithmetic, &c. ...

Includes index.

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

A new look at reversible logic implementation of decimal adder

Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates.

Performance Analysis of Reversible Fast Decimal Adders

This paper presents a performance analysis of reversible, fault tolerant VLSI implementations of carry select and hybrid decimal adders suitable for multi-digit BCD addition. The designs enable partial parallel processing of all digits that perform high-speed addition in decimal domain. When the number of digits is more than 25 the hybrid decimal adder can operate 5 times faster than conventional decimal adder using classical logic gates. The speed up factor of hybrid adder increases above 10 when the number of decimal digits is more than 25 for reversible logic implementation. Such highspeed decimal adders find applications in real time processors and internet-based applications. The implementations use only reversible conservative Fredkin gates, which make it suitable for VLSI circuits.

Quick Addition of Decimals Using Reversible Conservative Logic

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.

The elements of arithmetic ... in which decimal and integral arithmetic are combined, and taught inductively, on the system of Pestalozzi. Part 1st [2d].

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Efficient Implementation Of A Single-Precision Floating-Point Arithmetic Unit on FPGA

This paper presents a single precision floating point arithmetic unit with support for multiplication, addition, fused multiply-add, reciprocal, square-root and inverse squareroot with high-performance and low resource usage. The design uses a piecewise 2nd order polynomial approximation to implement reciprocal, square-root and inverse square-root. The unit can be configured with any number of operations and is capable to calculate any function with a throughput of one operation per cycle. The floatingpoint multiplier of the unit is also used to implement the polynomial approximation and the fused multiply-add operation. We have compared our implementation with other state-of-the-art proposals, including the Xilinx Core-Gen operators, and conclude that the approach has a high relative performance/area efficiency. © 2014 Technical University of Munich (TUM).

Arithmetic-based binary-to-RNS converter modulo {2(n)+/- k} for jn-Bit dynamic range

In this brief, a read-only-memoryless structure for binary-to-residue number system (RNS) conversion modulo {2(n) +/- k} is proposed. This structure is based only on adders and constant multipliers. This brief is motivated by the existing {2(n) +/- k} binary-to-RNS converters, which are particular inefficient for larger values of n. The experimental results obtained for 4n and 8n bits of dynamic range suggest that the proposed conversion structures are able to significantly improve the forward conversion efficiency, with an AT metric improvement above 100%, regarding the related state of the art. Delay improvements of 2.17 times with only 5% area increase can be achieved if a proper selection of the {2(n) +/- k} moduli is performed.

A cross-cultural study on the effect of decimal separator on price perception

A Work Project, presented as part of the requirements for the Award of a Masters Degree in Management from the NOVA – School of Business and Economics

On an upper bound for the arithmetic self-intersection number of the dualizing sheaf on arithmetic surfaces

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Higher arithmetic Chow groups

We give a new construction of higher arithmetic Chow groups for quasi-projective arithmetic varieties over a field. Our definition agrees with the higher arithmetic Chow groups defined by Goncharov for projective arithmetic varieties over a field. These groups are the analogue, in the Arakelov context, of the higher algebraic Chow groups defined by Bloch. The degree zero group agrees with the arithmetic Chow groups of Burgos. Our new construction is shown to be a contravariant functor and is endowed with a product structure, which is commutative and associative.

Singular Bott-Chern classes and the arithmetic Grothendieck-Riemann-Roch theorem for closed immersions

We study the singular Bott-Chern classes introduced by Bismut, Gillet and Soulé. Singular Bott-Chern classes are the main ingredient to define direct images for closed immersions in arithmetic K-theory. In this paper we give an axiomatic definition of a theory of singular Bott-Chern classes, study their properties, and classify all possible theories of this kind. We identify the theory defined by Bismut, Gillet and Soulé as the only one that satisfies the additional condition of being homogeneous. We include a proof of the arithmetic Grothendieck-Riemann-Roch theorem for closed immersions that generalizes a result of Bismut, Gillet and Soulé and was already proved by Zha. This result can be combined with the arithmetic Grothendieck-Riemann-Roch theorem for submersions to extend this theorem to arbitrary projective morphisms. As a byproduct of this study we obtain two results of independent interest. First, we prove a Poincaré lemma for the complex of currents with fixed wave front set, and second we prove that certain direct images of Bott-Chern classes are closed.

An irreducibility criterion for group representations, with arithmetic applications

We prove a criterion for the irreducibility of an integral group representation p over the fraction field of a noetherian domain R in terms of suitably defined reductions of p at prime ideals of R. As applications, we give irreducibility results for universal deformations of residual representations, with a special attention to universal deformations of residual Galois representations associated with modular forms of weight at least 2.

A survey on recent p-adic integration theories and arithmetic applications

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