Switching transients in ferroelectric dicalcium strontium propionate (DSP) and azoxybenzene

The switching transients in dicalcium strontium propionate and azoxybenzene were studied by the use of the Merz method. It was observed that the switching time depends linearly on the applied electric field. Under similar electric fields, the switching processes in DSP and azoxybenzene are slower than in triglycine sulphate (TGS) at 27°C.

Switching transients in ferroelectric dicalcium strontium propionate (DSP) and Azoxybenzene

The ferroelectric polarization switching was studied in DSP single crystal and Azoxybenzene liquid film using the method described by Merz (1954). The DSP single crystal samples were in the form of plates 0.5 mm - 1.0 mm thick. The Azoxybenzene liquid film samples had a thickness from 0.025 mm - 0.125 mm. Switching in DSP was observed in the temperature range +7°C to -30°C, while in Azoxybenzene it was observed from 30°C to 70°C.

High resolution mapping of Dense spike-ar (dsp.ar) to the genetic centromere of barley chromosome 7H

Spike density in barley is under the control of several major genes, as documented previously by genetic analysis of a number of morphological mutants. One such class of mutants affects the rachis internode length leading to dense or compact spikes and the underlying genes were designated dense spike (dsp). We previously delimited two introgressed genomic segments on chromosome 3H (21 SNP loci, 35.5 cM) and 7H (17 SNP loci, 20.34 cM) in BW265, a BC7F3 nearly isogenic line (NIL) of cv. Bowman as potentially containing the dense spike mutant locus dsp.ar, by genotyping 1,536 single nucleotide polymorphism (SNP) markers in both BW265 and its recurrent parent. Here, the gene was allocated by high-resolution bi-parental mapping to a 0.37 cM interval between markers SC57808 (Hv_SPL14)-CAPSK06413 residing on the short and long arm at the genetic centromere of chromosome 7H, respectively. This region putatively contains more than 800 genes as deduced by comparison with the collinear regions of barley, rice, sorghum and Brachypodium, Classical map-based isolation of the gene dsp.ar thus will be complicated due to the infavorable relationship of genetic to physical distances at the target locus.

Vector control of permanent magnet synchronous motor using DSP controller

PMSM drive with high dynamic response is the attractive solution for servo applications like robotics, machine tools, electric vehicles. Vector control is widely accepted control strategy for PMSM control, which enables decoupled control of torque and flux, this improving the transient response of torque and speed. As the vector control demands exhaustive real time computations, so the present work is implemented using TI DSP 320C240. Presently position and speed controller have been successfully tested. The feedback information used is shaft (rotor) position from the incremental encoder and two motor currents. We conclude with the hope to extend the present experimental set up for further research related to PMSM applications.

Developement of DSP based educational kit for power electronics and drives

The educational kit was developed for power electronics and drives. The need and purpose of this kit is to train engineers with current technology of digital control in power electronics. The DSP is the natural choice as it is able to perform high speed calculations required in power electronics. The educational kit consists of a DSP platform using TI DSP TMS320C50 starter kit, an inverter and an induction machine-dc machine set. A set of experiments have been prepared so that DSP programming can be learned easily in a smooth fashion. Here the application presented is open loop V/F control of three phase induction using sine pulse width modulation technique.

Dual-DSP system for signal and image processing

The design of a dual-DSP microprocessor system and its application for parallel FFT and two-dimensional convolution are explained. The system is based on a master-salve configuration. Two ADSP-2101s are configured as slave processors and a PC/AT serves as the master. The master serves as a control processor to transfer the program code and data to the DSPs. The system architecture and the algorithms for the two applications, viz. FFT and two-dimensional convolutions, are discussed.

Synthesis of ASIPs for DSP algorithms

ASICs offer the best realization of DSP algorithms in terms of performance, but the cost is prohibitive, especially when the volumes involved are low. However, if the architecture synthesis trajectory for such algorithms is such that the target architecture can be identified as an interconnection of elementary parameterized computational structures, then it is possible to attain a close match, both in terms of performance and power with respect to an ASIC, for any algorithmic parameters of the given algorithm. Such an architecture is weakly programmable (configurable) and can be viewed as an application specific integrated processor (ASIP). In this work, we present a methodology to synthesize ASIPs for DSP algorithms. (C) 1999 Elsevier Science B.V. All rights reserved.

Adaptive Filtering Technique and DSP Based Implementation for High-Speed Distance Protection

The paper presents an adaptive Fourier filtering technique and a relaying scheme based on a combination of a digital band-pass filter along with a three-sample algorithm, for applications in high-speed numerical distance protection. To enhance the performance of above-mentioned technique, a high-speed fault detector has been used. MATLAB based simulation studies show that the adaptive Fourier filtering technique provides fast tripping for near faults and security for farther faults. The digital relaying scheme based on a combination of digital band-pass filter along with three-sample data window algorithm also provides accurate and high-speed detection of faults. The paper also proposes a high performance 16-bit fixed point DSP (Texas Instruments TMS320LF2407A) processor based hardware scheme suitable for implementation of the above techniques. To evaluate the performance of the proposed relaying scheme under steady state and transient conditions, PC based menu driven relay test procedures are developed using National Instruments LabVIEW software. The test signals are generated in real time using LabVIEW compatible analog output modules. The results obtained from the simulation studies as well as hardware implementations are also presented.

Synthesis of configurable architectures for DSP algorithms

ASICs offer the best realization of DSP algorithms in terms of performance, but the cost is prohibitive, especially when the volumes involved are low. However, if the architecture synthesis trajectory for such algorithms is such that the target architecture can be identified as an interconnection of elementary parameterized computational structures, then it is possible to attain a close match, both in terms of performance and power with respect to an ASIC, for any algorithmic parameters of the given algorithm. Such an architecture is weakly programmable (configurable) and can be viewed as an application specific instruction-set processor (ASIP). In this work, we present a methodology to synthesize ASIPs for DSP algorithms.

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip

Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. In this article, we address the on-chip memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. In this paper we propose two different methods for physical memory architecture exploration and identify the strengths and applicability of these methods in a systematic way. Both methods address the memory architecture exploration for a given target application by considering the application's data access characteristics and generates a set of Pareto-optimal design points that are interesting from a power, performance and VLSI area perspective. To the best of our knowledge, this is the first comprehensive work on memory space exploration at physical memory level that integrates data layout and memory exploration to address the system objectives from both hardware design and application software development perspective. Further we propose an automatic framework that explores the design space identifying 100's of Pareto-optimal design points within a few hours of running on a standard desktop configuration.

嵌入式DSP系统中SDF模型资源优化技术研究

随着嵌入式DSP系统硬件的飞速发展，各种数据和控制流被应用到嵌入式DSP应用程序的计算机辅助设计中去。其中同步数据流(SDF)被广泛用于图形化的DSP设计环境。同步数据流的特点在于能够在编译时刻静态地确定一个有效的调度序列，从而减少运行时的开销。而对于资源短缺的DSP系统，如何优化同步数据流编译生成程序的内存和计算资源具有重要的意义。 对于内存资源优化，研究热点计算体单一出现调度(SAS)算法对于存在反馈环和数据密集处理的应用不可解或内存优化效果很差。文中提出了将SAS和Non-SAS类型调度算法相结合的层次化的存储优化方法。该方法定义了数据密集分量和强连通分量来描述环和数据密集处理结构，并依据数据优先消耗原则设计了启发式的Non-SAS调度算法对分量进行存储优化。该方法适用于任意SDF模型，并有良好的存储优化效果。实验结果证实了其有效性。 计算资源优化即SDF模型的并行计算。本文针对简单SDF模型，提出一种基于优先权的多处理调度方法。它为程序模块分级，采用高优先级优先执行的策略实现了SDF图的多处理器并行静态调度。相对于其他方法，它不需要把SDF图转换为先序图，所以具有更好的时间与空间复杂度。实验结果证实了该方法的有效性。 针对计算体数目多，输入输出速率大的复杂SDF模型，一种基于通信的快速多水平优化方法被提出。它把SDF模型转化为基于通信的数据流模型，并应用快速多水平优化算法对其进行分区，最后把分区映射到原SDF模型中。通过分析，它有良好的时间和空间复杂度，并且优化后的并行程序有较短的程序执行时间和较高的吞吐率。 综上，本文为嵌入式SDF模型的资源优化提供了完善的优化方法。

一种机载DSP系统主控机的实时计算模型

现代机载数字信号处理 (DSP)系统中的主控机是具有严格实时需求的计算环境 ,负责实时存储、显示和控制等重要功能 针对机载DSP系统的特殊性及其对实时计算的具体需求 ,提出了一种基于实时Linux技术的实时计算模型 它通过与操作系统层的实时支持相结合 ,实现了包括多任务并发的实时调度方法、硬实时和软实时任务协同工作机制以及实时事件驱动机制在内的完整运行环境 相对于现有的基于分时操作系统的方案 ,实时性能更为可靠 ,计算资源利用率高 ;相对于使用受严格许可证限制的商业实时操作系统的技术 ,应用开发灵活易行 ,软件成本更低

嵌入式DSP系统中SDF模型的层次化存储优化方法

在同步数据流模型(SDF)描述的嵌入式数字信号处理(DSP)系统中,计算体单一出现调度(SAS)算法对于存在反馈环和数据密集处理的应用不可解或内存优化效果很差.文中提出了将SAS和Non-SAS类型调度算法相结合的层次化的存储优化方法,定义了数据密集分量和强连通分量来描述环和数据密集处理结构,并依据数据优先消耗原则设计了启发式的Non-SAS调度算法对分量进行存储优化.该方法适用于任意SDF模型,并有良好的存储优化效果.实验结果证明了其有效性.