Définition des interactions entre l’immunité innée et adaptative pendant l’infection aiguë par le virus de l’hépatite C (VHC)

La majorité des individus exposés au virus de l’hépatite C (VHC) développent une infection chronique. Une réponse immunitaire adaptative forte et soutenue est associée avec la guérison spontanée du VHC, mais les mécanismes sous-jacents demeurent mal définis. Le rôle des cellules NK et des cellules dendritiques (DC) dans la guérison spontanée du VHC est encore méconnu. Les cellules NK sont la population effectrice la plus importante de l’immunité innée car elles tuent les cellules infectées et sécrètent diverses cytokines. Les DC reconnaissent des agents infectieux et elles sont les premières à initier et réguler l’immunité adaptative. Les cellules NK et les DC interagissent également entre elles afin de réguler l’immunité innée et adaptative. L’hypothèse du projet de doctorat est que l'activité des cellules NK pendant la phase aiguë de l'infection par le VHC module la fonction des DC afin que ces dernières puissent générer une réponse immunitaire adaptative capable d'éliminer le VHC. Le premier objectif était d’établir une corrélation entre l'activité des cellules NK et l'évolution de l'infection au VHC. Nous avons observé une augmentation de la cytotoxicité, mais une diminution de la sécrétion de cytokines par les cellules NK chez les patients chroniques et qui ont résolu spontanément pendant la phase aiguë en comparaison aux contrôles non infectés, démontrant alors une dissociation entre ces deux fonctions. Nos résultats suggèrent que les cellules NK sont activées pendant la phase aiguë indépendamment de l’évolution de l’infection. Le deuxième objectif était d’établir une corrélation entre le phénotype et la fonction des DC, et l'évolution de l'infection. Nous avons d’abord observé que les DC plasmacytoïdes de tous les patients infectés ont un phénotype plus immature que les contrôles, et que ce phénotype est plus prononcé chez les patients ayant résolu spontanément. De plus, en réponse à des stimulations, nous avons observé que pendant la phase aiguë précoce, les DC myéloïdes (mDC) de tous les patients infectés indépendamment de l’évolution de l’infection produisent davantage de cytokines en comparaison aux contrôles. Cependant, cette hyperréactivité n’est pas soutenue au cours de l’évolution chronique. Le troisième objectif était d’établir une corrélation entre les interactions NK/DC et l’évolution de l’infection. Nous avons étudié la capacité des cellules NK à lyser les DC potentiellement tolérogéniques, ainsi que la capacité des DC matures à activer les cellules NK, et nous avons observé aucune différence entre les patients infectés et les contrôles. Finalement, nous avons démontré pour la première fois la capacité des DC immatures à inhiber la fonction des cellules NK. En conclusion, nous avons démontré que les cellules NK sont activées pendant la phase aiguë de l’infection par le VHC indépendamment de l’évolution de l’infection. De plus, la capacité des cellules NK à éliminer les DC potentiellement tolérogéniques est intacte. Finalement, les mDC sont hyperréactives pendant la phase aiguë de l’infection, mais cette hyperréactivité n’est pas soutenue avec la persistance de l’infection. Cette perte d’hyperréactivité des mDC ne semble pas affecter la capacité des DC à activer les cellules NK, mais elle pourrait jouer un rôle dans l’inefficacité de l’immunité adaptative à éliminer le VHC.

Asymmetrical DC link voltage configuration for a diode-clamped inverter

There is a trade off between a number of output voltage levels and the reliability and efficiency of a multilevel converter. A new configuration of diode-clamped multilevel inverters with a different combination of DC link capacitors voltage has been proposed in this paper. Two different symmetrical and asymmetrical unequal arrangements for a four-level diode-clamped inverter have been compared, in order to find an optimum arrangement with lower switching losses and optimised output voltage quality. The simulation and hardware results for a four-level inverter show that the asymmetrical configuration can obtain more output voltage levels with the same number of components compared with a conventional four-level inverter and this will lead to the reduction of the harmonic content of the output voltage. A new family of multi-output DC-DC converters with a simple control strategy has been utilised as a front-end converter to supply the DC link capacitor voltages for the optimised configuration.

Multi-output DC-DC converters based on diode-clamped converters configuration : topology and control strategy

This paper presents a new DC-DC Multi-Output Boost (MOB) converter which can share its total output between different series of output voltages for low and high power applications. This configuration can be utilised instead of several single output power supplies. This is a compatible topology for a diode-clamed inverter in the grid connection systems, where boosting low rectified output-voltage and series DC link capacitors is required. To verify the proposed topology, steady state and dynamic analysis of a MOB converter are examined. A simple control strategy has been proposed to demonstrate the performance of the proposed topology for a double-output boost converter. The topology and its control strategy can easily be extended to offer multiple outputs. Simulation and experimental results are presented to show the validity of the control strategy for the proposed converter.

A new family of multi-output DC-DC converter topologies to supply an asymmetrical four-level diode-clamped inverter

Purpose Multi-level diode-clamped inverters have the challenge of capacitor voltage balancing when the number of DC-link capacitors is three or more. On the other hand, asymmetrical DC-link voltage sources have been applied to increase the number of voltage levels without increasing the number of switches. The purpose of this paper is to show that an appropriate multi-output DC-DC converter can resolve the problem of capacitor voltage balancing and utilize the asymmetrical DC-link voltages advantages. Design/methodology/approach A family of multi-output DC-DC converters is presented in this paper. The application of these converters is to convert the output voltage of a photovoltaic (PV) panel to regulate DC-link voltages of an asymmetrical four-level diode-clamped inverter utilized for domestic applications. To verify the versatility of the presented topology, simulations have been directed for different situations and results are presented. Some related experiments have been developed to examine the capabilities of the proposed converters. Findings The three-output voltage-sharing converters presented in this paper have been mathematically analysed and proven to be appropriate to improve the quality of the residential application of PV by means of four-level asymmetrical diode-clamped inverter supplying highly resistive loads. Originality/value This paper shows that an appropriate multi-output DC-DC converter can resolve the problem of capacitor voltage balancing and utilize the asymmetrical DC-link voltages advantages and that there is a possibility of operation at high-modulation index despite reference voltage magnitude and power factor variations.

Flexible high-power multi DC-DC converters for train systems

This thesis reports on the investigations, simulations and analyses of novel power electronics topologies and control strategies. The research is financed by an Australian Research Council (ARC) Linkage (07-09) grant. Therefore, in addition to developing original research and contributing to the available knowledge of power electronics, it also contributes to the design of a DC-DC converter for specific application to the auxiliary power supply in electric trains. Specifically, in this regard, it contributes to the design of a 7.5 kW DC-DC converter for the industrial partner (Schaffler and Associates Ltd) who supported this project. As the thesis is formatted as a ‘thesis by publication’, the contents are organized around published papers. The research has resulted in eleven papers, including seven peer reviewed and published conference papers, one published journal paper, two journal papers accepted for publication and one submitted journal paper (provisionally accepted subject to few changes). In this research, several novel DC-DC converter topologies are introduced, analysed, and tested. The similarity of all of the topologies devised lies in their ‘current circulating’ switching state, which allows them to store some energy in the inductor, as extra inductor current. The stored energy may be applied to enhance the performance of the converter in the occurrence of load current or input voltage disturbances. In addition, when there is an alternating load current, the ability to store energy allows the converter to perform satisfactorily despite frequently and highly varying load current. In this research, the capability of current storage has been utilised to design topologies for specific applications, and the enhancement of the performance of the considered applications has been illustrated. The simplest DC-DC converter topology, which has a ‘current circulating’ switching state, is the Positive Buck-Boost (PBB) converter (also known as the non-inverting Buck-Boost converter). Usually, the topology of the PBB converter is operating as a Buck or a Boost converter in applications with widely varying input voltage or output reference voltage. For example, in electric railways (the application of our industrial partner), the overhead line voltage alternates from 1000VDC to 500VDC and the required regulated voltage is 600VDC. In the course of this research, our industrial partner (Schaffler and Associates Ltd) industrialized a PBB converter–the ‘Mudo converter’–operating at 7.5 kW. Programming the onboard DSP and testing the PBB converter in experimental and nominal power and voltage was part of this research program. In the earlier stages of this research, the advantages and drawbacks of utilization of the ‘current circulating’ switching state in the positive Buck-Boost converter were investigated. In brief, the advantages were found to be robustness against input voltage and current load disturbances, and the drawback was extra conduction and switching loss. Although the robustness against disturbances is desirable for many applications, the price of energy loss must be minimized to attract attention to the utilization of the PBB converter. In further stages of this research, two novel control strategies for different applications were devised to minimise the extra energy loss while the advantages of the positive Buck-Boost converter were fully utilized. The first strategy is Smart Load Controller (SLC) for applications with pre-knowledge or predictability of input voltage and/or load current disturbances. A convenient example of these applications is electric/hybrid cars where a master controller commands all changes in loads and voltage sources. Therefore, the master controller has a pre-knowledge of the load and input voltage disturbances so it can apply the SLC strategy to utilize robustness of the PBB converter. Another strategy aiming to minimise energy loss and maximise the robustness in the face of disturbance is developed to cover applications with unexpected disturbances. This strategy is named Dynamic Hysteresis Band (DHB), and is used to manipulate the hysteresis band height after occurrence of disturbance to reduce dynamics of the output voltage. When no disturbance has occurred, the PBB converter works with minimum inductor current and minimum energy loss. New topologies based on the PBB converter have been introduced to address input voltage disturbances for different onboard applications. The research shows that the performance of applications of symmetrical/asymmetrical multi-level diode-clamped inverters, DC-networks, and linear-assisted RF amplifiers may be enhanced by the utilization of topologies based on the PBB converter. Multi-level diode-clamped inverters have the problem of DC-link voltage balancing when the power factor of their load closes to unity. This research has shown that this problem may be solved with a suitable multi-output DC-DC converter supplying DClink capacitors. Furthermore, the multi-level diode-clamped inverters supplied with asymmetrical DC-link voltages may improve the quality of load voltage and reduce the level of Electromagnetic Interference (EMI). Mathematical analyses and experiments on supplying symmetrical and asymmetrical multi-level inverters by specifically designed multi-output DC-DC converters have been reported in two journal papers. Another application in which the system performance can be improved by utilization of the ‘current circulating’ switching state is linear-assisted RF amplifiers in communicational receivers. The concept of ‘linear-assisted’ is to divide the signal into two frequency domains: low frequency, which should be amplified by a switching circuit; and the high frequency domain, which should be amplified by a linear amplifier. The objective is to minimize the overall power loss. This research suggests using the current storage capacity of a PBB based converter to increase its bandwidth, and to increase the domain of the switching converter. The PBB converter addresses the industrial demand for a DC-DC converter for the application of auxiliary power supply of a typical electric train. However, after testing the industrial prototype of the PBB converter, there were some voltage and current spikes because of switching. To attenuate this problem without significantly increasing the switching loss, the idea of Active Gate Signalling (AGS) is presented. AGS suggests a smart gate driver that selectively controls the switching process to reduce voltage/current spikes, without unacceptable reduction in the efficiency of switching.

Flying-capacitor-based chopper circuit for DC capacitor voltage balancing in diode-clamped multilevel inverter

This paper proposes a flying-capacitor-based chopper circuit for dc capacitor voltage equalization in diode-clamped multilevel inverters. Its important features are reduced voltage stress across the chopper switches, possible reduction in the chopper switching frequency, improved reliability, and ride-through capability enhancement. This topology is analyzed using three- and four-level flying-capacitor-based chopper circuit configurations. These configurations are different in capacitor and semiconductor device count and correspondingly reduce the device voltage stresses by half and one-third, respectively. The detailed working principles and control schemes for these circuits are presented. It is shown that, by preferentially selecting the available chopper switch states, the dc-link capacitor voltages can be efficiently equalized in addition to having tightly regulated flying-capacitor voltages around their references. The various operating modes of the chopper are described along with their preferential selection logic to achieve the desired performances. The performance of the proposed chopper and corresponding control schemes are confirmed through both simulation and experimental investigations.

Dwell-time and run-time control for DC mass rapid transit railways

Dwell times at stations and inter-station run times are the two major operational parameters to maintain train schedule in railway service. Current practices on dwell-time and run-time control are that they are only optimal with respect to certain nominal traffic conditions, but not necessarily the current service demand. The advantages of dwell-time and run-time control on trains are therefore not fully considered. The application of a dynamic programming approach, with the aid of an event-based model, to devise an optimal set of dwell times and run times for trains under given operational constraints over a regional level is presented. Since train operation is interactive and of multi-attributes, dwell-time and run-time coordination among trains is a multi-dimensional problem. The computational demand on devising trains' instructions, a prime concern in real-time applications, is excessively high. To properly reduce the computational demand in the provision of appropriate dwell times and run times for trains, a DC railway line is divided into a number of regions and each region is controlled by a dwell- time and run-time controller. The performance and feasibility of the controller in formulating the dwell-time and run-time solutions for real-time applications are demonstrated through simulations.

AC/DC electrical characteristics of epoxy-multi wall carbon nanotube nanocomposites

Expoxy nanocomposites with multiwell carbon nanotubes (mwcnts) filler up to 0.3%wt were prepared by sheer mixing and good dispersion of the MWCNTS in the epoxy was successfully achieved. The electrical behaviour was characterized by measurements of the alternating current (ac) and direct current (dc) conductives at room temperature. Typical percolation behaviour was observed at a low percolation threshold of 0.055%. Frequency independent ac conductivity was observed at low frequencies but not at high frequencies. An equivalent circuit models was used to predict the impedence response in these nanocomposites.

Corona ions from overhead transmission voltage powerlines : effect on DC e-field and ambient particle concentration levels

Along with their essential role in electricity transmission and distribution, some powerlines also generate large concentrations of corona ions. This study aimed at comprehensive investigation of corona ions, vertical dc e-field, ambient aerosol particle charge and particle number concentration levels in the proximity of some high/sub-transmission voltage powerlines. The influence of meteorology on the instantaneous value of these parameters, and the possible existence of links or associations between the parameters measured were also statistically investigated. The presence of positive and negative polarities of corona ions was associated with variation in the mean vertical dc e-field, ambient ion and particle charge concentration level. Though these variations increased with wind speed, their values also decreased with distance from the powerlines. Predominately positive polarities of ions were recorded up to a distance of 150 m (with the maximum values recorded 50 m downwind of the powerlines). At 200 m from the source, negative ions predominated. Particle number concentration levels however remained relatively constant (103 particle cm-3) irrespective of the sampling site and distance from the powerlines. Meteorological factors of temperature, humidity and wind direction showed no influence on the electrical parameters measured. The study also discovered that e-field measurements were not necessarily a true representation of the ground-level ambient ion/particle charge concentrations.

A new unequal DC link voltage configuration for a single phase multilevel converter to reduce low order harmonics

Multilevel converters are used in high power and high voltage applications due to their attractive benefits in generating high quality output voltage. Increasing the number of voltage levels can lead to a reduction in lower order harmonics. Various modulation and control techniques are introduced for multilevel converters like Space Vector Modulation (SVM), Sinusoidal Pulse Width Modulation (SPWM) and Harmonic Elimination (HE) methods. Multilevel converters may have a DC link with equal or unequal DC voltages. In this paper a new modulation technique based on harmonic elimination method is proposed for those multilevel converters that have unequal DC link voltages. This new technique has better effect on output voltage quality and less Total Harmonic Distortion (THD) than other modulation techniques. In order to verify the proposed modulation technique, MATLAB simulations are carried out for a single-phase diode-clamped inverter.

Common DC link in residential LV network to improve the penetration level of Small-Scale Embedded Generators

This paper presents a new approach for network upgrading to improve the penetration level of Small Scale Generators in residential feeders. In this paper, it is proposed that a common DC link can be added to LV network to alleviate the negative impact of increased export power on AC lines, allowing customers to inject their surplus power with no restrictions to the common DC link. In addition, it is shown that the proposed approach can be a pathway from current AC network to future DC network.

Harmonic elimination technique for a single-phase multilevel converter with unequal DC link voltage levels

Multilevel converters, because of the benefits they attract in generating high quality output voltage, are used in several applications. Various modulation and control techniques are introduced by several researchers to control the output voltage of the multilevel converters like space vector modulation and harmonic elimination (HE) methods. Multilevel converters may have a DC link with equal or unequal DC voltages. In this study a new HE technique based on the HE method is proposed for multilevel converters with unequal DC link voltage. The DC link voltage levels are considered as additional variables for the HE method and the voltage levels are defined based on the HE results. Increasing the number of voltage levels can reduce lower order harmonic content because of the fact that more variables are created. In comparison to previous methods, this new technique has a positive effect on the output voltage quality by reducing its total harmonic distortion, which must take into consideration for some applications such as uninterruptable power supply, motor drive systems and piezoelectric transducer excitation. In order to verify the proposed modulation technique, MATLAB simulations and experimental tests are carried out for a single-phase four-level diode-clamped converter.

Control of dc capacitor voltages in diode-clamped multilevel inverter using bidirectional buck-boost choppers

The dc capacitors voltage unbalancing is the main technical drawback of a diode-clamped multilevel inverter (DCMLI), with more than three levels. A voltage-balancing circuit based on buck–boost chopper connected to the dc link of DCMLI is a reliable and robust solution to this problem. This study presents four different schemes for controlling the chopper circuit to achieve the capacitor voltages equalisation. These can be broadly categorised as single-pulse, multi-pulse and hysteresis band current control schemes. The single-pulse scheme does not involve faster switching actions but need the chopper devices to be rated for higher current. The chopper devices current rating can be kept limited by using the multi-pulse scheme but it involves faster switching actions and slower response. The hysteresis band current control scheme offers faster dynamics, lower current rating of the chopper devices and can nullify the initial voltage imbalance as well. However, it involves much faster switching actions which may not be feasible for some of its applications. Therefore depending on the system requirements and ratings, one of these schemes may be used. The performance and validity of the proposed schemes are confirmed through both simulation and experimental investigations on a prototype five-level diode-clamped inverter.