Simulations of parasitic and intrinsic capacitances related to Multiple-Gate-Field-Effect Transistor architectures

Report for the scientific sojourn carried out at the Université Catholique de Louvain, Belgium, from March until June 2007. In the first part, the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET) is deeply analyzed using finite element simulations. Several architectures such as single gate, FinFETs (double gate), triple-gate represented by Pi-gate MOSFETs are simulated and compared in terms of channel and fringing capacitances for the same occupied die area. Simulations highlight the great impact of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when Selective Epitaxial Growth (SEG) technology is introduced. The impact of these technological solutions on the transistor cut-off frequencies is also discussed. The second part deals with the study of the effect of the volume inversion (VI) on the capacitances of undoped Double-Gate (DG) MOSFETs. For that purpose, we present simulation results for the capacitances of undoped DG MOSFETs using an explicit and analytical compact model. It monstrates that the transition from volume inversion regime to dual gate behaviour is well simulated. The model shows an accurate dependence on the silicon layer thickness,consistent withtwo dimensional numerical simulations, for both thin and thick silicon films. Whereas the current drive and transconductance are enhanced in volume inversion regime, our results show thatintrinsic capacitances present higher values as well, which may limit the high speed (delay time) behaviour of DG MOSFETs under volume inversion regime.

Dense carbon monoliths for supercapacitors with outstanding volumetric capacitances

A commercially available dense carbon monolith (CM) and four carbon monoliths obtained from it have been studied as electrochemical capacitor electrodes in a two-electrode cell. CM has: (i) very high density (1.17 g cm−3), (ii) high electrical conductivity (9.3 S cm−1), (iii) well-compacted and interconnected carbon spheres, (iv) homogeneous microporous structure and (v) apparent BET surface area of 957 m2g−1. It presents interesting electrochemical behaviors (e.g., excellent gravimetric capacitance and outstanding volumetric capacitance). The textural characteristics of CM (porosity and surface chemistry) have been modified by means of different treatments. The electrochemical performances of the starting and treated monoliths have been analyzed as a function of their porous textures and surface chemistry, both on gravimetric and volumetric basis. The monoliths present high specific and volumetric capacitances (292 F g−1 and 342 F cm−3), high energy densities (38 Wh kg−1 and 44 Wh L−1), and high power densities (176 W kg−1 and 183 W L−1). The specific and volumetric capacitances, especially the volumetric capacitance, are the highest ever reported for carbon monoliths. The high values are achieved due to a suitable combination of density, electrical conductivity, porosity and oxygen surface content.

The effect of linear loading capacitances upon the switching transient of colemanite.

"NAVORD report 5922, NOLC report 413."

Characteristics of small-signal capacitances of silicon-on-sapphire MOSFETs

The measured inter-electrode capacitances of silicon-on-sapphire (SOS) MOSFETs are presented and compared with simulation results. It is shown that the variations of capacitances with DC bias differ from those of bulk MOSFETs due to change in body potential variation of the SOS device resulting from electron-hole pair generation through impact ionisation.

Trapezoidal SOI FinFET analog parameters` dependence on cross-section shape

The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (A V), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies.

A DC-DC Step-Up mu-Power Converter for Energy Harvesting Applications, Using Maximum Power PointTracking, Based on Fractional Open Circuit Voltage

A DC-DC step-up micro power converter for solar energy harvesting applications is presented. The circuit is based on a switched-capacitorvoltage tripler architecture with MOSFET capacitors, which results in an, area approximately eight times smaller than using MiM capacitors for the 0.131mu m CMOS technology. In order to compensate for the loss of efficiency, due to the larger parasitic capacitances, a charge reutilization scheme is employed. The circuit is self-clocked, using a phase controller designed specifically to work with an amorphous silicon solar cell, in order to obtain themaximum available power from the cell. This will be done by tracking its maximum power point (MPPT) using the fractional open circuit voltage method. Electrical simulations of the circuit, together with an equivalent electrical model of an amorphous silicon solar cell, show that the circuit can deliver apower of 1132 mu W to the load, corresponding to a maximum efficiency of 66.81%.

Effects of sulphurization time on Cu2ZnSnS4 absorbers and thin films solar cells obtained from metallic precursors

We report the results of a study of the sulphurization time effects on Cu2ZnSnS4 absorbers and thin film solar cells prepared from dc-sputtered tackedmetallic precursors. Three different time intervals, 10 min, 30min and 60 min, at maximum sulphurization temperature were considered. The effects of this parameter' change were studied both on the absorber layer properties and on the final solar cell performance. The composition, structure, morphology and thicknesses of the CZTS layers were analyzed. The electrical characterization of the absorber layer was carried out by measuring the transversal electrical resistance of the samples as a function of temperature. This study shows an increase of the conductivity activation energy from 10 meV to 54meV for increasing sulphurization time from 10min to 60min. The solar cells were built with the following structure: SLG/Mo/CZTS/CdS/i-ZnO/ZnO:Al/Ni:Al grid. Several ac response equivalent circuit models were tested to fit impedance measurements. The best results were used to extract the device series and shunt resistances and capacitances. Absorber layer's electronic properties were also determined using the Mott–Schottky method. The results show a decrease of the average acceptor doping density and built-in voltage, from 2.0 1017 cm−3 to 6.5 1015 cm−3 and from 0.71 V to 0.51 V, respectively, with increasing sulphurization time. These results also show an increase of the depletion region width from approximately 90 nm–250 nm.

Solid-State bipolar Marx modulator modeling

A mathematical model that simulates the operation of a solid-state bipolar Marx modulator topology, including the influence of parasitic capacitances is presented and discussed as a tool to analyze the circuit behavior and to assist the design engineer to select the semiconductor components and to enhance the operating performance. Simulations show good agreement with experimental results, considering a four stage circuit assembled with 1200 V isolated gate bipolar transistors and diodes, operating at 1000 V dc input voltage and 1-kHz frequency, giving 4 kV and 10-mu s output pulses into several resistive loads. Results show that parasitic capacitances between Marx cells to ground can significantly load the solid-state switches, adding new operating circuit conditions.

Development of fractional order capacitors based on electrolyte processes

In recent years, significant research in the field of electrochemistry was developed. The performance of electrical devices, depending on the processes of the electrolytes, was described and the physical origin of each parameter was established. However, the influence of the irregularity of the electrodes was not a subject of study and only recently this problem became relevant in the viewpoint of fractional calculus. This paper describes an electrolytic process in the perspective of fractional order capacitors. In this line of thought, are developed several experiments for measuring the electrical impedance of the devices. The results are analyzed through the frequency response, revealing capacitances of fractional order that can constitute an alternative to the classical integer order elements. Fractional order electric circuits are used to model and study the performance of the electrolyte processes.

Design of switched-capacitor filters using low gain amplifiers

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores

Applicability of Power-Line Communications to Data Transfer of On-line Condition Monitoring of Electrical Drives

The research of power-line communications has been concentrated on home automation, broadband indoor communications and broadband data transfer in a low voltage distribution network between home andtransformer station. There has not been carried out much research work that is focused on the high frequency characteristics of industrial low voltage distribution networks. The industrial low voltage distribution network may be utilised as a communication channel to data transfer required by the on-line condition monitoring of electric motors. The advantage of using power-line data transfer is that it does not require the installing of new cables. In the first part of this work, the characteristics of industrial low voltage distribution network components and the pilot distribution network are measured and modelled with respect topower-line communications frequencies up to 30 MHz. The distributed inductances, capacitances and attenuation of MCMK type low voltage power cables are measured in the frequency band 100 kHz - 30 MHz and an attenuation formula for the cables is formed based on the measurements. The input impedances of electric motors (15-250 kW) are measured using several signal couplings and measurement based input impedance model for electric motor with a slotted stator is formed. The model is designed for the frequency band 10 kHz - 30 MHz. Next, the effect of DC (direct current) voltage link inverter on power line data transfer is briefly analysed. Finally, a pilot distribution network is formed and signal attenuation in communication channels in the pilot environment is measured. The results are compared with the simulations that are carried out utilising the developed models and measured parameters for cables and motors. In the second part of this work, a narrowband power-line data transfer system is developed for the data transfer ofon-line condition monitoring of electric motors. It is developed using standardintegrated circuits. The system is tested in the pilot environment and the applicability of the system for the data transfer required by the on-line condition monitoring of electric motors is analysed.

Selluloosapohjaisten superkondensaattorien valmistaminen hiilinanoputkista

Tämän työn tarkoitus on seuloa oleelliset prosessiparametrit superkondensaattoreiden elektrodikomposiittien valmistuksessa, jotka vaikuttavat kondensaattorin laatuun. Tarkoitus on tutkia parametreja, joiden avulla prosessia on mahdollista optimoida. Työn tarkoituksena on tutkia myös itse komponenttimateriaalien valmistusvaiheen sekoitusprosessia mitatulla ja laskennallisella seokseen siirtyvällä tehonkulutuksella. Työn kirjallisuusosassa esitetään superkondensaattoreiden rakennetta, toimintamekanismia ja ominaisuuksia sähköenergian varastoijana. Lisäksi tarkastellaan tavallisimpia kondensaattoreihin sisältyviä materiaaleja, erityisesti hiilinanoputkia ja selluloosakuituja. Sekoitusprosesseista tarkastellaan kokeellisessa osassa käytettävien sekoituslaitteita ja niiden toimintamekanismeja komponenttien sekoitusprosesseissa. Kokeellisessa osassa tutkimuskysymyksiksi asetettiin eri sekoitusparametrien (materiaalin määrä ja laatu sekä sekoitusajat) vaikutus superkondensaattorien elektrodiarkkien ominaiskapasitansseihin. Testit suoritettiin LUT Prosessien laboratoriossa, ja testeissä massojen sekoitukseen käytettiin roottoristaattoria ja ultraäänisekoitinta. Lisäksi tutkittiin prosessin skaalausta varten skaalatulla laitteistolla sekoitettuja massanäytteitä. Sekoitusprosessin riittävyyttä varten tutkittiin kokeellisesti käytettyjen sekoituslaitteiden tehonkulutusta. Lisäksi roottoristaattorille tehtiin laskentaohjelmalla virtaussimulaatio paikallisen tehonkulutuksen selvittämiseksi Testeissä todettiin tutkittujen parametrien vaikutus, mutta tulosten perusteella varsinaista optimointia ei kyetty tekemään. Tulokset kuitenkin antavat suunnan, johon prosessia voi optimointia varten kehittää. Myös sekoitukseen todettiin siirtyvän suuri määrä tehoa tutkituilla laitteilla, mitä voidaan pitää mahdollisesti riittävänä käytettyjen komponenttien sekoitukseen.

Discrete demand side control performance under dynamic building simulation: a heat pump application

This study presents the findings of applying a Discrete Demand Side Control (DDSC) approach to the space heating of two case study buildings. High and low tolerance scenarios are implemented on the space heating controller to assess the impact of DDSC upon buildings with different thermal capacitances, light-weight and heavy-weight construction. Space heating is provided by an electric heat pump powered from a wind turbine, with a back-up electrical network connection in the event of insufficient wind being available when a demand occurs. Findings highlight that thermal comfort is maintained within an acceptable range while the DDSC controller maintains the demand/supply balance. Whilst it is noted that energy demand increases slightly, as this is mostly supplied from the wind turbine, this is of little significance and hence a reduction in operating costs and carbon emissions is still attained.

Analytical calculation of resonant inductance for zero voltage switching in phase-shifted full-bridge converters

The phase shift full bridge (PSFB) converter allows high efficiency power conversion at high frequencies through zero voltage switching (ZVS); the parasitic drain-to-source capacitance of the MOSFET is discharged by a resonant inductance before the switch is gated resulting in near zero turn-on switching losses. Typically, an extra inductance is added to the leakage inductance of a transformer to form the resonant inductance necessary to charge and discharge the parasitic capacitances of the PSFB converter. However, many PSFB models do not consider the effects of the magnetizing inductance or dead-time in selecting the resonant inductance required to achieve ZVS. The choice of resonant inductance is crucial to the ZVS operation of the PSFB converter. Incorrectly sized resonant inductance will not achieve ZVS or will limit the load regulation ability of the converter. This paper presents a unique and accurate equation for calculating the resonant inductance required to achieve ZVS over a wide load range incorporating the effects of the magnetizing inductance and dead-time. The derived equations are validated against PSPICE simulations of a PSFB converter and extensive hardware experimentations.