A novel self consistent calculation approach for the capacitance-voltage characteristics of semiconductor quantum wire transistors based on a split-gate configuration

Purpose - The purpose of this paper is to develop an efficient numerical algorithm for the self-consistent solution of Schrodinger and Poisson equations in one-dimensional systems. The goal is to compute the charge-control and capacitance-voltage characteristics of quantum wire transistors. Design/methodology/approach - The paper presents a numerical formulation employing a non-uniform finite difference discretization scheme, in which the wavefunctions and electronic energy levels are obtained by solving the Schrodinger equation through the split-operator method while a relaxation method in the FTCS scheme ("Forward Time Centered Space") is used to solve the two-dimensional Poisson equation. Findings - The numerical model is validated by taking previously published results as a benchmark and then applying them to yield the charge-control characteristics and the capacitance-voltage relationship for a split-gate quantum wire device. Originality/value - The paper helps to fulfill the need for C-V models of quantum wire device. To do so, the authors implemented a straightforward calculation method for the two-dimensional electronic carrier density n(x,y). The formulation reduces the computational procedure to a much simpler problem, similar to the one-dimensional quantization case, significantly diminishing running time.

Interface properties and capacitance-voltage behaviour of diamond devices prepared by microwave-assisted CVD

Free standing diamond films were used to study the effect of diamond surface morphology and microstructure on the electrical properties of Schottky barrier diodes. By using free standing films both the rough top diamond surface and the very smooth bottom surface are available for post-metal deposition. Rectifying electrical contacts were then established either with the smooth or the rough surface. The estimate of doping density from the capacitance-voltage plots shows that the smooth surface has a lower doping density when compared with the top layers of the same film. The results also show that surface roughness does not contribute significantly to the frequency dispersion of the small signal capacitance. The electrical properties of an abrupt asymmetric n(+)(silicon)-p(diamond) junction have also been measured. The I-V curves exhibit at low temperatures a plateau near zero bias, and show inversion of rectification. Capacitance-voltage characteristics show a capacitance minimum with forward bias, which is dependent on the environment conditions. It is proposed that this anomalous effect arises from high level injection of minority carriers into the bulk.

Interface properties and capacitance-voltage behaviour of diamond devices prepared by microwave-assisted CVD

Free standing diamond films were used to study the effect of diamond surface morphology and microstructure on the electrical properties of Schottky barrier diodes. By using free standing films both the rough top diamond surface and the very smooth bottom surface are available for post-metal deposition. Rectifying electrical contacts were then established either with the smooth or the rough surface. The estimate of doping density from the capacitance-voltage plots shows that the smooth surface has a lower doping density when compared with the top layers of the same film. The results also show that surface roughness does not contribute significantly to the frequency dispersion of the small signal capacitance. The electrical properties of an abrupt asymmetric n(+)(silicon)-p(diamond) junction have also been measured. The I-V curves exhibit at low temperatures a plateau near zero bias, and show inversion of rectification. Capacitance-voltage characteristics show a capacitance minimum with forward bias, which is dependent on the environment conditions. It is proposed that this anomalous effect arises from high level injection of minority carriers into the bulk.

Simulation of interface states effect on the scanning capacitance microscopy measurement of p-n junctions

A two-dimensional numerical simulation model of interface states in scanning capacitance microscopy (SCM) measurements of p-n junctions is presented-In the model, amphoteric interface states with two transition energies in the Si band gap are represented as fixed charges to account for their behavior in SCM measurements. The interface states are shown to cause a stretch-out-and a parallel shift of the capacitance-voltage characteristics in the depletion. and neutral regions of p-n junctions, respectively. This explains the discrepancy between - the SCM measurement and simulation near p-n junctions, and thus modeling interface states is crucial for SCM dopant profiling of p-n junctions. (C) 2002 American Institute of Physics.

Study of metal oxide-semiconductor capacitors with rf magnetron sputtering TiO(x) and TiO(x)N(y) gate dielectric layer

Metal oxide-semiconductor capacitors with TiO(x) deposited with different O(2) partial pressures (30%, 35%, and 40%) and annealed at 550, 750, and 1000 degrees C were fabricated and characterized. Fourier transform infrared, x-ray near edge spectroscopy, and elipsometry measurements were performed to characterize the TiO(x) films. TiO(x)N(y) films were also obtained by adding nitrogen to the gaseous mixture and physical results were presented. Capacitance-voltage (1 MHz) and current-voltage measurements were utilized to obtain the effective dielectric constant, effective oxide thickness, leakage current density, and interface quality. The results show that the obtained TiO(x) films present a dielectric constant varying from 40 to 170 and a leakage current density (for V(G)=-1 V, for some structures as low as 1 nA/cm(2), acceptable for complementary metal oxide semiconductor circuits fabrication), indicating that this material is a viable, in terms of leakage current density, highk substitute for current ultrathin dielectric layers. (C) 2009 American Vacuum Society. [DOI: 10.1116/1.3043537]

Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs

The impact of the titanium nitride (TIN) gate electrode thickness has been investigated in n and p channel SOI multiple gate field effect transistors (MuGFETs) through low frequency noise charge pumping and static measurements as well as capacitance-voltage curves The results suggest that a thicker TIN metal gate electrode gives rise to a higher EOT a lower mobility and a higher interface trap density The devices have also been studied for different back gate biases where the GIFBE onset occurs at lower front-gate voltage for thinner TIN metal gate thickness and at higher V(GF) In addition it is demonstrated that post deposition nitridation of the MOCVD HfSiO gate dielectric exhibits an unexpected trend with TIN gate electrode thickness where a continuous variation of EOT and an increase on the degradation of the interface quality are observed (C) 2010 Elsevier Ltd All rights reserved

Study of reactive sputtering titanium oxide for metal-oxide-semiconductor capacitors

Metal oxide semiconductor (MOS) capacitors with titanium oxide (TiO(x)) dielectric layer, deposited with different oxygen partial pressure (30,35 and 40%) and annealed at 550, 750 and 1000 degrees C, were fabricated and characterized. Capacitance-voltage and current-voltage measurements were utilized to obtain, the effective dielectric constant, effective oxide thickness, leakage current density and interface quality. The obtained TiO(x) films present a dielectric constant varying from 40 to 170 and a leakage current density, for a gate voltage of - 1 V, as low as 1 nA/cm(2) for some of the structures, acceptable for MOS fabrication, indicating that this material is a viable high dielectric constant substitute for current ultra thin dielectric layers. (C) 2009 Elsevier B.V. All rights reserved.

Low-temperature deposition of silicon oxide and silicon nitride by reactive magnetron sputtering

In this study, oxide and nitride films were deposited at room temperature through the reaction of silicon Sputtered by argon and oxygen ions or argon and nitrogen ions at 250 and 350 W with 0.67 Pa pressure. It was observed that for both thin films the deposition rates increase with the applied RF power and decrease with the increase of the gas concentration. The Si/O and Si/N ratio were obtained through RBS analyses and for silicon oxide the values changed from 0.42 to 0.57 and for silicon nitride the Values changed from 0.4 to 1.03. The dielectric constants were calculated through capacitance-voltage curves with the silicon oxide values varying from 2.4 to 5.5, and silicon nitride values varying from 6.2 to 6.7, which are good options for microelectronic dielectrics. (c) 2008 Elsevier Ltd. All rights reserved.

Bias dependent photocurrent collection in p-i-n a-Si : EVSiC : H heterojunction

A series of large area single layers and heterojunction cells in the assembly glass/ZnO:Al/p (SixC1-x:H)/i (Si:H)/n (SixC1-x:H)/Al (0 capacitance-voltage characteristics. For the heterojunction cells S-shaped J-V characteristics under different illumination conditions are observed leading to poor fill factors. High serial resistances around 10(5)Ohm are also measured Simulated results confirm the experimental findings suggesting that the transport in dark depends almost exclusively on field-aided drift while under illumination it is dependent mainly on minority carriers the diffusion.

Bias-dependent photocurrent collection in p-i-n a-Si : H/SiC : H heterojunction

A series of large area single layers and glass/ZnO:AVp(SixC1-x:H)/i(Si:H)/n(SixC1-x:H)/AI (0 < x < 1) heterojunction cells were produced by plasma-enhanced chemical vapour deposition (PE-CVD) at low temperature. Junction properties, carrier transport and photogeneration are investigated from dark and illuminated current-voltage (J-V) and capacitance-voltage (C-V) characteristics. For the heterojunction cells atypical J-V characteristics under different illumination conditions are observed leading to poor fill factors. High series resistances around 106 Q are also measured. These experimental results were used as a basis for the numerical simulation of the energy band diagram, and the electrical field distribution of the structures. Further comparison with the sensor performance gave satisfactory agreement. Results show that the conduction band offset is the most limiting parameter for the optimal collection of the photogenerated carriers. As the optical gap increases and the conductivity of the doped layers decreases, the transport mechanism changes from a drift to a diffusion-limited process.

ITO/SiOx/Si optical sensor with internal gain

A visible/near-infrared optical sensor based on an ITO/SiOx/n-Si structure with internal gain is presented. This surface-barrier structure was fabricated by a low-temperature processing technique. The interface properties and carder transport were investigated from dark current-voltage and capacitance-voltage characteristics. Examination of the multiplication properties was performed under different light excitation and reverse bias conditions. The spectral and pulse response characteristics are analysed. The current amplification mechanism is interpreted by the control of electron current by the space charge of photogenerated holes near the SiOx/Si interface. The optical sensor output characteristics and some possible device applications are presented.

Photodiode with nanocrystalline Si/amorphous Si absorber bilayer

This letter reports a near-ultraviolet/visible/near-infrared n(+)-n-i-delta(i)-p photodiode with an absorber comprising a nanocrystalline silicon n layer and a hydrogenated amorphous silicon i layer. Device modeling reveals that the dominant source of reverse dark current is deep defect states in the n layer, and its magnitude is controlled by the i layer thickness. The photodiode with the 900/400 nm thick n-i layers exhibits a reverse dark current density of 3nA/cm(2) at -1V. Donor concentration and diffusion length of holes in the n layer are estimated from the capacitance-voltage characteristics and from the bias dependence of long-wavelength response, respectively. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3660725]

A comparison between thin film solar cells made from co-evaporated CuIn1-xGaxSe2using a one-stage process versus a three-stage process

Until this day, the most efficient Cu(In,Ga)Se2 thin film solar cells have been prepared using a rather complex growth process often referred to as three-stage or multistage. This family of processes is mainly characterized by a first step deposited with only In, Ga and Se flux to form a first layer. Cu is added in a second step until the film becomes slightly Cu-rich, where-after the film is converted to its final Cu-poor composition by a third stage, again with no or very little addition of Cu. In this paper, a comparison between solar cells prepared with the three-stage process and a one-stage/in-line process with the same composition, thickness, and solar cell stack is made. The one-stage process is easier to be used in an industrial scale and do not have Cu-rich transitions. The samples were analyzed using glow discharge optical emission spectroscopy, scanning electron microscopy, X-ray diffraction, current–voltage-temperature, capacitance-voltage, external quantum efficiency, transmission/reflection, and photoluminescence. It was concluded that in spite of differences in the texturing, morphology and Ga gradient, the electrical performance of the two types of samples is quite similar as demonstrated by the similar J–V behavior, quantum spectral response, and the estimated recombination losses.

Microdoping compensation of microcrystalline silicon obtained by Hot-Wire Chemical Vapour Deposition

Undoped hydrogenated microcrystalline silicon was obtained by hot-wire chemical vapour deposition at different silane-to-hydrogen ratios and low temperature (<300 °C). As well as technological aspects of the deposition process, we report structural, optical and electrical characterizations of the samples that were used as the active layer for preliminary p-i-n solar cells. Raman spectroscopy indicates that changing the hydrogen dilution can vary the crystalline fraction. From electrical measurements an unwanted n-type character is deduced for this undoped material. This effect could be due to a contaminant, probably oxygen, which is also observed in capacitance-voltage measurements on Schottky structures. The negative effect of contaminants on the device was dramatic and a compensated p-i-n structure was also deposited to enhance the cell performance.

Research and development of III-V semiconductor surfaces for improved device interfaces

This thesis is devoted to understanding and improving technologically important III-V compound semiconductor (e.g. GaAs, InAs, and InSb) surfaces and interfaces for devices. The surfaces and interfaces of crystalline III-V materials have a crucial role in the operation of field-effect-transistors (FET) and highefficiency solar-cells, for instance. However, the surfaces are also the most defective part of the semiconductor material and it is essential to decrease the amount of harmful surface or interface defects for the next-generation III-V semiconductor device applications. Any improvement in the crystal ordering at the semiconductor surface reduces the amount of defects and increases the material homogeneity. This is becoming more and more important when the semiconductor device structures decrease to atomic-scale dimensions. Toward that target, the effects of different adsorbates (i.e., Sn, In, and O) on the III-V surface structures and properties have been investigated in this work. Furthermore, novel thin-films have been synthesized, which show beneficial properties regarding the passivation of the reactive III-V surfaces. The work comprises ultra-high-vacuum (UHV) environment for the controlled fabrication of atomically ordered III-V(100) surfaces. The surface sensitive experimental methods [low energy electron diffraction (LEED), scanning tunneling microscopy/spectroscopy (STM/STS), and synchrotron radiation photoelectron spectroscopy (SRPES)] and computational density-functionaltheory (DFT) calculations are utilized for elucidating the atomic and electronic properties of the crucial III-V surfaces. The basic research results are also transferred to actual device tests by fabricating metal-oxide-semiconductor capacitors and utilizing the interface sensitive measurement techniques [capacitance voltage (CV) profiling, and photoluminescence (PL) spectroscopy] for the characterization. This part of the thesis includes the instrumentation of home-made UHV-compatible atomic-layer-deposition (ALD) reactor for growing good quality insulator layers. The results of this thesis elucidate the atomic structures of technologically promising Sn- and In-stabilized III-V compound semiconductor surfaces. It is shown that the Sn adsorbate induces an atomic structure with (1×2)/(1×4) surface symmetry which is characterized by Sn-group III dimers. Furthermore, the stability of peculiar ζa structure is demonstrated for the GaAs(100)-In surface. The beneficial effects of these surface structures regarding the crucial III-V oxide interface are demonstrated. Namely, it is found that it is possible to passivate the III-V surface by a careful atomic-scale engineering of the III-V surface prior to the gate-dielectric deposition. The thin (1×2)/(1×4)-Sn layer is found to catalyze the removal of harmful amorphous III-V oxides. Also, novel crystalline III-V-oxide structures are synthesized and it is shown that these structures improve the device characteristics. The finding of crystalline oxide structures is exploited by solving the atomic structure of InSb(100)(1×2) and elucidating the electronic structure of oxidized InSb(100) for the first time.