The ZVS-PWM commutation cell applied to the DC-AC converter

This paper presents the analysis of a dc-ac converter using a zero-voltage-switching (ZVS) commutation cell. First, we show the cell applied to the buck converter. The stages of operation are presented along with the main current and voltage equations. Next, we adapt the converter to the regenerative-operation mode. Hence, the full-bridge converter at low-frequency operation is connected in the dc-dc output stage (at high frequency). The main switches commute at zero voltage. The converter operated at constant frequency with pulse-width modulation (PWM), and neither overvoltage nor additional current stress was observed by digital simulation. A design example and experimental results obtained by prototype, rated at 275 V and 1 kW, are also presented. © 1997 IEEE.

A HPF AC-AC converter for Permanent Magnet Generator applications

This paper describes the design and development of a high input power-factor (HPF) AC to AC converter for naval applications using Permanent Magnet Generator (PMG). The proposed converter comprises an isolated three-phase uncontrolled multipulse rectification stage directly connected to a single-phase inverter stage, without the use of DC to DC intermediary stage, resulting in more simplicity for the overall circuitry, assuring robustness, reliability and reduced costs. Furthermore, the multipulse rectifier stage is capable to provide high power factor and input currents with low total harmonic distortion (THD). The output voltage of the PMG varies from 260V rms (220 Hz) to 380V rms (360 Hz), depending on load conditions. The output single-phase inverter stage was designed to operate with wide range of DC bus voltage, maintaining 120V rms, 60 Hz output. Measured total harmonic distortion for the AC output voltage represents less than 2%, at 3.6kW nominal linear load. © 2010 IEEE.

Voltage Sensing Using an Asynchronous Charge-to-Digital Converter for Energy-Autonomous Environments

In future systems with relatively unreliable and unpredictable energy sources such as harvesters, the system power supply may become non-deterministic. For energy effective operations, Vdd is an important parameter in any meaningful system control mechanism. Reliable and accurate on-chip voltage sensors are therefore indispensible for the power and computation management of such systems. Existing voltage sensing methods are not suitable because they usually require a stable and known reference (voltage, current, time, frequency, etc.), which is difficult to obtain in this environment. This paper describes an autonomous reference-free voltage sensor designed using an asynchronous counter powered by the charge on a capacitor and a small controller. Unlike existing methods, the voltage information is directly generated as a digital code. The sensor, fabricated in the 180 nm technology node, was tested successfully through performing measurements over the voltage range from 1.8 V down to 0.8 V.

A novel Sigma–Delta based parallel analogue-to-residue converter

Animportant step in the residue number system(RNS) based signal processing is the conversion of signal into residue domain. Many implementations of this conversion have been proposed for various goals, and one of the implementations is by a direct conversion from an analogue input. A novel approach for analogue-to-residue conversion is proposed in this research using the most popular Sigma–Delta analogue-to-digital converter (SD-ADC). In this approach, the front end is the same as in traditional SD-ADC that uses Sigma–Delta (SD) modulator with appropriate dynamic range, but the filtering is doneby a filter implemented usingRNSarithmetic. Hence, the natural output of the filter is an RNS representation of the input signal. The resolution, conversion speed, hardware complexity and cost of implementation of the proposed SD based analogue-to-residue converter are compared with the existing analogue-to-residue converters based on Nyquist rate ADCs

A non-linear analogue-to-digital converter for linearization of transducer input-output relationships

Analogue and digital techniques for linearization of non-linear input-output relationship of transducers are briefly reviewed. The condition required for linearizing a non-linear function y = f(x) using a non-linear analogue-to-digital converter, is explained. A simple technique to construct a non-linear digital-to-analogue converter, based on ' segments of equal digital interval ' is described. The technique was used to build an N-DAC which can be employed in a successive approximation or counter-ramp type ADC to linearize the non-linear transfer function of a thermistor-resistor combination. The possibility of achieving an order of magnitude higher accuracy in the measurement of temperature is shown.

Pipeline Analog To Ternary Converter

The paper describes the application of the pipelining principle to the realization of an analogue-to-ternary converter. The circuit shows a considerable saving in hard-ware compared with an earlier proposed circuit. The main hardware components used are analogue comparators, subtractors and the delay elements; hence this method of A/T conversion can operate at a higher sampling frequency.

A dual-slope analogue-to-digital converter for generating polynomials

A new digital polynomial generator using the principle of dual-slope analogue-to-digital conversion is proposed. Techniques for realizing a wide range of integer as well as fractional coefficients to obtain the desired polynomial have been discussed. The suitability of realizing the proposed polynomial generator in integrated circuit form is also indicated.

A rule-based grapheme-to-phone converter for TTS systems in european portuguese

In this paper, a linguistically rule-based grapheme-to-phone (G2P) transcription algorithm is described for European Portuguese. A complete set of phonological and phonetic transcription rules regarding the European Portuguese standard variety is presented. This algorithm was implemented and tested by using online newspaper articles. The obtained experimental results gave rise to 98.80% of accuracy rate. Future developments in order to increase this value are foreseen. Our purpose with this work is to develop a module/ tool that can improve synthetic speech naturalness in European Portuguese. Other applications of this system can be expected like language teaching/learning. These results, together with our perspectives of future improvements, have proved the dramatic importance of linguistic knowledge on the development of Text-to-Speech systems (TTS).

An algorithmic of analog-to-digital converter using current-mode and digital CMOS process

In this paper a new algorithmic of Analog-to-Digital Converter is presented. This new topology use the current-mode technique that allows a large dynamic range and can be implemented in digital CMOS process. The ADC proposed is very small and can handle high sampling rates. Simulation results using a 1.2um CMOS process show that an 8-b ADC can support a sampling rate of 50MHz.

Time to digital converter

In questa tesi è analizzato il caso di sensori con uscita in frequenza e periodo, si traduce in ultima analisi nella capacità di misurare con precisione un intervallo temporale. La rivelazione del tempo risulta essere lo stadio fondamentale da cui deriva la risoluzione dell'intero sistema di misura. Nella realtà, la questione della simultaneità cioè individuare con assoluta precisione due eventi che si verificano contemporaneamente, in un determinato istante t, è un problema piuttosto complesso: le difficoltà sono correlate soprattutto alle limitazioni fisiche intrinseche degli strumenti di misura. E' utile allora fornire un'analisi sui principi e le tecniche alla base della misura di intervalli temporali, detta Time Interval Measurement (TIM). Lo scopo della tesi è studiare i vari metodi per realizzare TDC lineari digitali, facendo un'analisi critica e ed evidenziando pro e contro che i vari approcci presentano, attingendo e analizzando criticamente informazioni dalle varie fonti riportate in bibliografia.

Accurate Analysis of Subharmonic Oscillations of V^2 and V^2Ic Controls Applied to Buck Converter

V2Ic control provides very fast dynamic performance to the Buck converter both under load steps and under voltage reference steps. However, the design of this control is complex since it is prone to subharmonic oscillations and several parameters affect the stability of the system. This paper derives and validates a very accurate modeling and stability analysis of a closed-loop V2Ic control using the Floquet theory. This allows the derivation of sensitivity analysis to design a robust converter. The proposed methodology is validated on a 5-MHz Buck converter. The work is also extended to V2 control using the same methodology, showing high accuracy and robustness. The paper also demonstrates, on the V2 control, that even a low bandwidth-linear controller can affect the stability of a ripple-based control.

RASER: random to serial converter.

"COO 1469-0209."