The value of a small microkernel for dreamy memory and the RAMpage memory hierarchy

This paper explores potential for the RAMpage memory hierarchy to use a microkernel with a small memory footprint, in a specialized cache-speed static RAM (tightly-coupled memory, TCM). Dreamy memory is DRAM kept in low-power mode, unless referenced. Simulations show that a small microkernel suits RAMpage well, in that it achieves significantly better speed and energy gains than a standard hierarchy from adding TCM. RAMpage, in its best 128KB L2 case, gained 11% speed using TCM, and reduced energy 14%. Equivalent conventional hierarchy gains were under 1%. While 1MB L2 was significantly faster against lower-energy cases for the smaller L2, the larger SRAM's energy does not justify the speed gain. Using a 128KB L2 cache in a conventional architecture resulted in a best-case overall run time of 2.58s, compared with the best dreamy mode run time (RAMpage without context switches on misses) of 3.34s, a speed penalty of 29%. Energy in the fastest 128KB L2 case was 2.18J vs. 1.50J, a reduction of 31%. The same RAMpage configuration without dreamy mode took 2.83s as simulated, and used 2.39J, an acceptable trade-off (penalty under 10%) for being able to switch easily to a lower-energy mode.

Test strategies on functionally partitioned module-based programmable architecture for base-band processing

A specialised reconfigurable architecture for telecommunication base-band processing is augmented with testing resources. The routing network is linked via virtual wire hardware modules to reduce the area occupied by connecting buses. The number of switches within the routing matrices is also minimised, which increases throughput without sacrificing flexibility. The testing algorithm was developed to systematically search for faults in the processing modules and the flexible high-speed routing network within the architecture. The testing algorithm starts by scanning the externally addressable memory space and testing the master controller. The controller then tests every switch in the route-through switch matrix by making loops from the shared memory to each of the switches. The local switch matrix is also tested in the same way. Next the local memory is scanned. Finally, pre-defined test vectors are loaded into local memory to check the processing modules. This algorithm scans all possible paths within the interconnection network exhaustively and reports all faults. Strategies can be inserted to bypass minor faults

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware Implementations

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniques for maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables, and an approach for performing parallel addition of N input symbols.

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware : Implementations,Parallelization Prospectsand Possible Improvements

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniquesfor maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables,and an approach for performing parallel addition of N input symbols.

Il était une fois une cible et un distracteur : électrophysiologie des mécanismes corticaux de l'attention visuelle en perception et en mémoire.

Cet ouvrage explore en trois volets des aspects du traitement attentionnel de cibles et de distracteurs visuels ainsi que leur mesures électrophysiologiques. Le premier chapitre aborde le traitement attentionnel spécifique à la cible et aux distracteurs durant une recherche visuelle. La division de la N2pc en une NT et une PD remet en question la théorie proposant qu'il existe systématiquement une activité attentionnelle liée à un distracteur saillant, car un distracteur vert ne provoque aucune activité latéralisée propre. Le second chapitre aborde la question de la latéralisation des structures responsables du maintient et de la récupération d'information en mémoire visuelle à court-terme. En utilisant un paradigme de latéralisation de la cible et du distracteur, il nous est possible de vérifier qu'il existe une composante latéralisée négative dans la région temporale, la TCN, propre à la cible lors du rappel en mémoire. De plus, on observe également une composante latéralisée pour le distracteur sur la partie postérieure du crâne. Ces deux éléments convergent pour indiquer qu'il existe une latéralisation des structures activées lors de la récupération de l'information en mémoire visuelle à court-terme en fonction de l'hémichamps où se trouve la cible ou le distracteur. Enfin, dans le troisième chapitre, il est question de l'effet sur le déploiement attentionnel de l'ajout de distracteurs gris de faible saillance autour de cibles potentielles. L'ajout de ces distracteurs augmente la difficulté d'identification de la cible. Cette difficulté provoque un déplacement de l'activité de la N2pc vers la fenêtre de temps associée à la composante Ptc. Un nombre plus important de distracteurs gris entraîne une plus grande proportion de l'activité à être retardée. Également, les distracteurs gris qui sont placés entre les cibles potentielles provoquent un retard plus important que les distracteurs placés hors de cette région. Au cours de cette thèse, la question de la saillance attentionnelle des différentes couleurs durant une recherche visuelle est récurente. Nous observons une plus grande saillance du rouge par rapport au vert quand ils sont distracteurs et le vert est plus difficile à distinguer du gris que le jaune.

Language context modulates reading route: an electrical neuroimaging study.

INTRODUCTION The orthographic depth hypothesis (Katz and Feldman, 1983) posits that different reading routes are engaged depending on the type of grapheme/phoneme correspondence of the language being read. Shallow orthographies with consistent grapheme/phoneme correspondences favor encoding via non-lexical pathways, where each grapheme is sequentially mapped to its corresponding phoneme. In contrast, deep orthographies with inconsistent grapheme/phoneme correspondences favor lexical pathways, where phonemes are retrieved from specialized memory structures. This hypothesis, however, lacks compelling empirical support. The aim of the present study was to investigate the impact of orthographic depth on reading route selection using a within-subject design. METHOD We presented the same pseudowords (PWs) to highly proficient bilinguals and manipulated the orthographic depth of PW reading by embedding them among two separated German or French language contexts, implicating respectively, shallow or deep orthography. High density electroencephalography was recorded during the task. RESULTS The topography of the ERPs to identical PWs differed 300-360 ms post-stimulus onset when the PWs were read in different orthographic depth context, indicating distinct brain networks engaged in reading during this time window. The brain sources underlying these topographic effects were located within left inferior frontal (German > French), parietal (French > German) and cingular areas (German > French). CONCLUSION Reading in a shallow context favors non-lexical pathways, reflected in a stronger engagement of frontal phonological areas in the shallow versus the deep orthographic context. In contrast, reading PW in a deep orthographic context recruits less routine non-lexical pathways, reflected in a stronger engagement of visuo-attentional parietal areas in the deep versus shallow orthographic context. These collective results support a modulation of reading route by orthographic depth.

Heap analysis in the presence of collection libraries

Memory analysis techniques have become sophisticated enough to model, with a high degree of accuracy, the manipulation of simple memory structures (finite structures, single/double linked lists and trees). However, modern programming languages provide extensive library support including a wide range of generic collection objects that make use of complex internal data structures. While these data structures ensure that the collections are efficient, often these representations cannot be effectively modeled by existing methods (either due to excessive analysis runtime or due to the inability to represent the required information). This paper presents a method to represent collections using an abstraction of their semantics. The construction of the abstract semantics for the collection objects is done in a manner that allows individual elements in the collections to be identified. Our construction also supports iterators over the collections and is able to model the position of the iterators with respect to the elements in the collection. By ordering the contents of the collection based on the iterator position, the model can represent a notion of progress when iteratively manipulating the contents of a collection. These features allow strong updates to the individual elements in the collection as well as strong updates over the collections themselves.

Endowing NoSQL DBMS with SQL features through standard Call Level Interfaces

To store, update and retrieve data from database management systems (DBMS), software architects use tools, like call-level interfaces (CLI), which provide standard functionalities to interact with DBMS. However, the emerging of NoSQL paradigm, and particularly new NoSQL DBMS providers, lead to situations where some of the standard functionalities provided by CLI are not supported, very often due to their distance from the relational model or due to design constraints. As such, when a system architect needs to evolve, namely from a relational DBMS to a NoSQL DBMS, he must overcome the difficulties conveyed by the features not provided by NoSQL DBMS. Choosing the wrong NoSQL DBMS risks major issues with components requesting non-supported features. This paper focuses on how to deploy features that are not so commonly supported by NoSQL DBMS (like Stored Procedures, Transactions, Save Points and interactions with local memory structures) by implementing them in standard CLI.

Vibration control with shape-memory alloys in civil engineering structures

Dissertação apresentada à Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Doutor em Engenharia Civil

Enhanced resistive switching and multilevel behavior in bilayered HfAlO/HfAlOx structures for non-volatile memory applications

In this work, hafnium aluminum oxide (HfAlO) thin films were deposited by ion beam sputtering deposition technique on Si substrate. The presence of oxygen vacancies in the HfAlOx layer deposited in oxygen deficient environment is evidenced from the photoluminescence spectra. Furthermore, HfAlO(oxygen rich)/HfAlOx(oxygen poor) bilayer structures exhibit multilevel resistive switching (RS), and the switching ratio becomes more prominent with increasing the HfAlO layer thickness. The bilayer structure with HfAlO/HfAlOx thickness of 30/40 nm displays the enhanced multilevel resistive switching characteristics, where the high resistance state/ intermediate resistance state (IRS) and IRS/low resistance state resistance ratios are 102 and 5 105 , respectively. The switching mechanisms in the bilayer structures were investigated by the temperature dependence of the three resistance states. This study revealed that the multilevel RS is attributed to the coupling of ionic conduction and the metallic conduction, being the first associated to the formation and rupture of conductive filaments related to oxygen vacancies and the second with the formation of a metallic filament. Moreover, the bilayer structures exhibit good endurance and stability in time.

Kollektiivista muistia etsimässä : How Collectivities Remember : Structures and Spaces of Social and Cultural Memory

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Pregnenolone sulfate enhances post-training memory processes when injected in very low doses into limbic system structures: the amygdala is by far the most sensitive.

Immediate post-training, stereotactically guided, intraparenchymal administration of pregnenolone sulfate (PS) into the amygdala, septum, mammillary bodies, or caudate nucleus and of PS, dehydroepiandrosterone sulfate, and corticosterone into the hippocampus was performed in mice that had been weakly trained in a foot-shock active avoidance paradigm. Intrahippocampal injection of PS resulted in memory enhancement (ME) at a lower dose than was found with dehydroepiandrosterone sulfate and corticosterone. Intraamygdally administered PS was approximately 10(4) times more potent on a molar basis in producing ME than when PS was injected into the hippocampus and approximately 10(5) times more potent than when injected into the septum or mammillary bodies. ME did not occur on injection of PS into the caudate nucleus over the range of doses tested in the other brain structures. The finding that fewer than 150 molecules of PS significantly enhanced post-training memory processes when injected into the amygdala establishes PS as the most potent memory enhancer yet reported and the amygdala as the most sensitive brain region for ME by any substance yet tested.