Rapid prototyping of polymeric electrophoresis microchips with integrated copper electrodes for contactless conductivity detection

A simple and easy approach to produce polymeric microchips with integrated copper electrodes for capacitively coupled contactless conductivity detection (CD) is described. Copper electrodes were fabricated using a printed circuit board (PCB) as an inexpensive thin-layer of metal. The electrode layout was first drawn and laser printed on a wax paper sheet. The toner layer deposited on the paper sheet was thermally transferred to the PCB surface working as a mask for wet chemical etching of the copper layer. After the etching step, the toner was removed with an acetonitrile-dampened cotton. A poly(ethylene terephthalate) (PET) film coated with a thin thermo-sensitive adhesive layer was used to laminate the PCB plate providing an insulator layer of the electrodes to perform CID measurements. Electrophoresis microchannels were fabricated in poly(dimethylsiloxane) (PDMS) by soft lithography and reversibly sealed against the PET film. These hybrid PDMS/PET chips exhibited a stable electroosmotic mobility of 4.25 +/- 0.04 x 10(-4) V cm(-2) s(-1), at pH 6.1, over fifty runs. Efficiencies ranging from 1127 to 1690 theoretical plates were obtained for inorganic cations.

MEMS-based incandescent microlamps for integrated optics applications

In this work we present the fabrication and operation of incandescent microlamps for integrated optics applications. This microlamp emits white and infrared light from a chromium resistor embedded in a free-standing silicon oxynitride (SiO(x)N(y)) cantilever that can be coupled to an optical waveguide. In fact, the chromium resistor is sandwiched between layers of SiO(x)N(y) that isolate it from the atmosphere, while electric current heats the resistor to incandescent temperatures. The same SiO(x)N(y) material used in the microlamp fabrication is also used to produce the optical waveguides to allow a monolithic integration of light source and optical circuit. Front-side bulk micromachining of the silicon substrate in potassium hydroxide (KOH) solution is used to fabricate the cantilevers that thermally isolate the resistors from the substrate, thus reducing the heat transfer and the current required to light the lamp.

Serotonergic mechanisms of the median raphe nucleus-dorsal hippocampus in conditioned fear: Output circuit involves the prefrontal cortex and amygdala

Independent studies have shown that the median raphe nucleus (MRN) and dorsal hippocampus (DH) are involved in the expression of contextual conditioned fear (CFC). However, studies that examine the integrated involvement of serotonergic mechanisms of the MRN-DH are lacking. To address this issue, a CFC paradigm was used to test whether the serotonergic projections from the MRN to DH can influence CFC. Serotoninergic drugs were infused either into the MRN or DH prior to testing sessions in which freezing and startle responses were measured in the same context where 6 h previously rats received footshocks. A reduction of serotonin (5-HT) transmission in the MRN by local infusions of the 5-HT(1A) agonist 8-hydroxy-2-(di-n-propylamino)-tetralin (8-OH-DPAT) decreased freezing in response to the context but did not reduce fear-potentiated startle. This pattern of results is consistent with the hypothesis that MRN serotonergic mechanisms selectively modulate the freezing response to the aversive context. As for the DH, a decrease in postsynaptic 5-HT receptor activity at projection areas has been proposed to be the main consequence of 5-HT(1A) receptor activation in the MIRN. Intra-DH injections of 8-OH-DPAT inhibited both the freezing and fear-potentiated startle response to the context. To reconcile these findings, an inhibitory mechanism may exist between the incoming 5-HT pathway from the MRN to DH and the neurons of the DH output to other structures. The DH-amygdala or medial prefrontal cortex projections could well be this output circuit modulating the expression of CFC as revealed by measurements of Fos immunoreactivity in these areas. (C) 2009 Elsevier B.V. All rights reserved.

A Voltage Limiter Circuit for Indoor Light Energy Harvesting Applications

A voltage limiter circuit for indoor light energy harvesting applications is presented. This circuit is a part of a bigger system, whose function is to harvest indoor light energy, process it and store it, so that it can be used at a later time. This processing consists on maximum power point tracking (MPPT) and stepping-up, of the voltage from the photovoltaic (PV) harvester cell. The circuit here described, ensures that even under strong illumination, the generated voltage will not exceed the limit allowed by the technology, avoiding the degradation, or destruction, of the integrated die. A prototype of the limiter circuit was designed in a 130 nm CMOS technology. The layout of the circuit has a total area of 23414 mu m(2). Simulation results, using Spectre, are presented.

Integrated photonic filters based on SiC multilayer structures

Combined tunable WDM converters based on SiC multilayer photonic active filters are analyzed. The operation combines the properties of active long-pass and short-pass wavelength filter sections into a capacitive active band-pass filter. The sensor element is a multilayered heterostructure produced by PE-CVD. The configuration includes two stacked SiC p-i-n structures sandwiched between two transparent contacts. Transfer function characteristics are studied both theoretically and experimentally. Results show that optical bias activated photonic device combines the demultiplexing operation with the simultaneous photodetection and self amplification of an optical signal acting the device as an integrated photonic filter in the visible range. Depending on the wavelength of the external background and irradiation side, the device acts either as a short- or a long-pass band filter or as a band-stop filter. The output waveform presents a nonlinear amplitude-dependent response to the wavelengths of the input channels. A numerical simulation and a two building-blocks active circuit are presented and give insight into the physics of the device. (c) 2013 Elsevier B.V. All rights reserved.

A 5GHz/1.8V CMOS Active Balun Integrated with LNA

The development of high performance monolithic RF front-ends requires innovative RF circuit design to make the best of a good technology. A fully differential approach is usually preferred, due to its well-known properties. Although the differential approach must be preserved inside the chip, there are cases where the input signal is single-ended such as RF image filters and IF filters in a RF receiver. In these situations, a stage able to convert single-ended into differential signals (balun) is needed. The most cited topology, which is capable of providing high gain, consists on a differential stage with one of the two inputs grounded. Unfortunately, this solution has some drawbacks when implemented monolithically. This work presents the design and simulated results of an innovative high-performance monolithic single to differential converter, which overcomes the limitations of the circuits.The integration of the monolithic active balun circuit with an LNA on a 0.18μm CMOS process is also reported. The circuits presented here are aimed at 802.11a. Section 2 describes the balun circuit and section 3 presents its performance when it is connected to a conventional single-ended LNA. Section 4 shows the simulated performance results focused at phase/amplitude balance and noise figure. Finally, the last section draws conclusions and future work.

Automated design of microwave discrete tuning differential capacitance circuits in Si-integrated technologies

A genetic algorithm used to design radio-frequency binary-weighted differential switched capacitor arrays (RFDSCAs) is presented in this article. The algorithm provides a set of circuits all having the same maximum performance. This article also describes the design, implementation, and measurements results of a 0.25 lm BiCMOS 3-bit RFDSCA. The experimental results show that the circuit presents the expected performance up to 40 GHz. The similarity between the evolutionary solutions, circuit simulations, and measured results indicates that the genetic synthesis method is a very useful tool for designing optimum performance RFDSCAs.

Transimpedance amplifier for integrated SpO2 optic sensor

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores

An RF LC Q-enhanced CMOS iter using integrated inductors with layout optimization

Dissertação apresentada para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores, pela Universidade Nova de Lisboa, Faculdade de Ciências e Tecnologia

Gated Geiger mode avalanche photodiode pixels with integrated readout electronics for low noise photon detection

Avalanche photodiodes operated in the Geiger mode offer a high intrinsic gain as well as an excellent timing accuracy. These qualities make the sensor specially suitable for those applications where detectors with high sensitivity and low timing uncertainty are required. Moreover, they are compatible with standard CMOS technologies, allowing sensor and front-end electronics integration within the pixel cell. However, the sensor suffers from high levels of intrinsic noise, which may lead to erroneous results and limit the range of detectable signals. They also increase the amount of data that has to be stored. In this work, we present a pixel based on a Geiger-mode avalanche photodiode operated in the gated mode to reduce the probability to detect noise counts interfering with photon arrival events. The readout circuit is based on a two grounds scheme to enable low reverse bias overvoltages and consequently lessen the dark count rate. Experimental characterization of the fabricated pixel with the HV-AMS 0.35µm standard technology is also presented in this article.

Active micromachined integrated terahertz circuits

Schottky barrier diodes have been integrated into on-chip rectangular waveguides. Two novel techniques have been developed to fabricate diodes with posts suitable for integration into waveguides. One technique produces diodes with anode diameters of the order of microns with post heights from 90 to 125 microns and the second technique produces sub-micron anodes with post heights around 20 microns. A method has been developed to incorporate these structures into a rectangular waveguide and provide a top contact onto the anode which could be used as an I.F. output in a mixer circuit. Devices have been fabricated and D.C. characterized.

A multisampling time-domain CMOS imager with synchronous readout circuit

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

A multisampling time-domain CMOS imager with synchronous readout circuit

A novel multisampling time-domain architecture for CMOS imagers with synchronous readout and wide dynamic range is proposed. The architecture was implemented in a prototype of imager with 32x32 pixel array fabricated in AMS CMOS 0.35νm and was characterized for sensitivity and color response. The pixel is composed of an n+/psub photodiode, a comparator and a D flip-flop having 16% fill-factor and 30νmx26νm dimensions. The multisampling architecture requires only a 1 bit per pixel memory instead of 8 bits which is typical for time-domain active pixel architectures. The advantage is that the number of transistors in the pixel is low, saving area and providing higher fill-factor. The maximum frame rate is analyzed as a function of number of bits and array size. The analysis shows that it is possible to achieve high frame rates and operation in video mode with 10 bits. Also, we present analysis for the impact of comparator offset voltage in the fixed pattern noise. Copyright 2007 ACM.

Integrated planning of electric power distribution networks

In this work, a heuristic model for integrated planning of primary distribution network and secondary distribution circuits is proposed. A Tabu Search (TS) algorithm is employed to solve the planning of primary distribution networks. Evolutionary Algorithms (EA) are used to solve the planning model of secondary networks. The planning integration of both networks is carried out by means a constructive heuristic taking into account a set of integration alternatives between these networks. These integration alternatives are treated in a hierarchical way. The planning of primary networks and secondary distribution circuits is carried out based on assessment of the effects of the alternative solutions in the expansion costs of both networks simultaneously. In order to evaluate this methodology, tests were performed for a real-life distribution system taking into account the primary and secondary networks.