Neuro-Stimulus Chip with Photodiodes Array for Sub-retinal Implants

A prototype neuro-stimulus chip for sub-retinal implants in blind patients affected by Age-related Macular Degeneration (AMD) or Retinitis Pigmentosa (RP) is presented in this paper. This retinal prosthetic chip was designed to replace the degenerated photoreceptor cells, and in order to stimulate directly the remaining healthy layers of retinal neurons. The current stimulus circuits are monolithic integrated with photodiodes (PD) array, which can convert the illumination on the eyes into bi-phasic electrical pulses. In addition, a novel charge cancellation circuit is used to discharge the electrodes for medical safty. The prototype chip is designed and fabricated in HJTC 0.18 mu m N-well CMOS 1P6M Mix-signal process, with a +/- 2.5 V dual voltage power supply.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

基于TPM的可信文件系统CIVFS的研究和实现

本文提出一种利用可信计算技术增强文件系统可信性的方法，以Linux为基础，设计实现了一个可信文件系统原型CIVFS。CIVFS是一个结合加密和完整性校验两种保护措施的文件系统，它借助堆式文件系统技术，嵌入在Linux内核中，添加了文件加密和完整性校验模块，利用TPM芯片提供的可信计算和安全存储等功能，增强了对系统安全组件和数据的安全保护。

基于TPM的可信文件系统CIVFS的研究和实现

本文提出一种利用可信计算技术增强文件系统可信性的方法，以Linux为基础，设计实现了一个可信文件系统原型CIVFS。CIVFS是一个结合加密和完整性校验两种保护措施的文件系统，它借助堆式文件系统技术，嵌入在Linux内核中，添加了文件加密和完整性校验模块，利用TPM芯片提供的可信计算和安全存储等功能，增强了对系统安全组件和数据的安全保护。

一种基于TPM匿名证书的信任协商方案

为促进分布式网络环境中跨安全域的信息共享与协作，需要一种合理有效的信任协商敏感信息保护机制．可信计算组织(Trusted Computing Group，TCG)专注于从计算平台体系结构上增强其安全性．基于可信计算的匿名证书机制提出一种新的信任协商方案：匿名证书信任协商ACTN(anonymous credentials based trusted negotiation)，良好地解决了跨安全域的敏感信息保护的问题，可以有效地防止重放攻击、窜改攻击和替换攻击．使用一个硬件模块TPM进行隐私信息保护，并通过TPM模块提供可靠的匿名证书和平台认证．定义了ACTN的模型以及模型中的匿名证书，详细说明了匿名证书的基本参数以及匿名证书的创建方法，讨论了策略的安全性、委托机制以及证书链的发现机制，同时设计了 协商节点的框架以及协商过程．通过实验并与TrustBuilder和COTN协商系统进行比较，表明系统具有良好的稳定性和可用性．最后指出相关的一些未来研究方向．

Uniform mems chip temperatures in the nucleate boiling heat transfer region by selecting suitable, medium boiling number range

The not only lower but also uniform MEMS chip temperatures can he reached by selecting suitable boiling number range that ensures the nucleate boiling heat transfer. In this article, boiling heat transfer experiments in 10 silicon triangular microchannels with the hydraulic diameter of 55.4 mu m were performed using acetone as the working fluid, having the inlet liquid temperatures of 24-40 degrees C, mass fluxes of 96-360 kg/m(2)s, heat fluxes of 140-420 kW/m(2), and exit vapor mass qualities of 0.28-0.70. The above data range correspond to the boiling number from 1.574 x 10(-3) to 3.219 x 10(-3) and ensure the perfect nucleate boiling heat transfer region, providing a very uniform chip temperature distribution in both streamline and transverse directions. The boiling heat transfer coefficients determined by the infrared radiator image system were found to he dependent on the heat Axes only, not dependent on the mass Axes and the vapor mass qualities covering the above data range. The high-speed flow visualization shows that the periodic flow patterns take place inside the microchannel in the time scale of milliseconds, consisting of liquid refilling stage, bubble nucleation, growth and coalescence stage, and transient liquid film evaporation stage in a full cycle. The paired or triplet bubble nucleation sites can occur in the microchannel corners anywhere along the flow direction, accounting for the nucleate boiling heat transfer mode. The periodic boiling process is similar to a series of bubble nucleation, growth, and departure followed by the liquid refilling in a single cavity for the pool boiling situation. The chip temperature difference across the whole two-phase area is found to he small in a couple of degrees, providing a better thermal management scheme for the high heat flux electronic components. Chen's [11 widely accepted correlation for macrochannels and Bao et al.'s [21 correlation obtained in a copper capillary tube with the inside diameter of 1.95 mm using R11 and HCFC123 as working fluids can predict the present experimental data with accepted accuracy. Other correlations fail to predict the correct heat transfer coefficient trends. New heat transfer correlations are also recommended.

On-Chip All-Optical Passive 3.55 Gbit/s NRZ-to-PRZ Format Conversion Using a High-Q Silicon-Based Microring Resonator

We report the experimental result of all-optical passive 3.55 Gbit/s non-return-to-zero (NRZ) to pseudo-return-to-zero (PRZ) format conversion using a high-quality-factor (Q-factor) silicon-based microring resonator notch filter on chip. The silicon-based microring resonator has 23800 Q-factor and 22 dB extinction ratio (ER), and the PRZ signals has about 108 ps width and 4.98 dB ER.

An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

An asymmetric MOSFET-C band-pass filter(BPF)with on chip charge pump auto-tuning is presented.It is implemented in UMC (United Manufacturing Corporation)0.18μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump OUtputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point(HP3) is 16.621 dBm,wim 50 Ω as the source impedance. The input referred noise iS about 47.455μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm~2 and it can be utilized in GPS (global positioning system)and Bluetooth systems.

Modified Holographic Exposure to Fabricate Varied Bragg Grating in an Identical Chip

A new fabricating method is demonstrated to realize two different Bragg gratings in an identical chip using traditional holographic exposure. Polyimide is used to protect one Bragg grating during the first period. The technical process of this method is as simple as that of standard holographic exposure

Multiple Quantum Well SEED Arrays for Flip-Chip Bonding Optoelectronic Smart Pixels

于2010-11-23批量导入

Optoelectronic Smart Pixels Comprising Flip-Chip-Bonded GaAs/AlGaAs MQW Detectors and Modulators on Silicon CMOS Circuit

于2010-11-23批量导入

16-channel VCSEL based multiple chip modules