The Spartan-3E tutorial 3 : using the LCD display [version 1.0]

This tutorial is designed to assist users who wish to use the LCD screen on the Spartan-3E board. In this tutorial, the PicoBlaze microcontroller is used to control the LCD. The tutorial is organised into three Parts. In Part A, code is written to display the message "Hello World" on the LCD. Part B demonstrates how to define and display custom characters. Finally, Part C shows how the display can be shifted and flashed. Shifting is done by using a delay in the main PicoBlaze program loop, while flashing is done using the PicoBlaze interrupt. The slider switches can be used to select the shifting direction, and to turn shifting and flashing on and off.

The Spartan-3E Tutorial 1 : Introduction to FPGA Programming, Version 2.0

This tutorial is designed to help new users become familiar with using the Spartan-3E board. The tutorial steps through: writing a small program in VHDL which carries out simple combinational logic; connecting the program inputs and outputs to the switches, buttons and LEDs on the Spartan-3E board; downloading the program to the Spartan-3E board using version 14.7 of the Xilinx ISE; and simulating the program using the iSim Simulator.

The harnessing of peptide-monolith constructs for single step plasmid DNA purification

The availability of synthetic peptides has paved the way for their use in tailor-made interactions with biomolecules. In this study, a 16mer LacI-based peptide was used as an affinity ligand to examine the scale up feasibility for plasmid DNA purification. First, the peptide was designed and characterized for the affinity purification of lacO containing plasmid DNA, to be employed as a high affinity ligand for the potential capturing of plasmid DNA in a single unit operation. It was found there were no discernible interactions with a control plasmid that did not encode the lacO nucleotide sequence. The dissociation equilibrium constant of the binding between the 16mer peptide and target pUC19 was 5.0 ± 0.5 × 10-8 M as assessed by surface plasmon resonance. This selectivity and moderated affinity indicate that the 16mer is suitable for the adsorption and chromatographic purification of plasmid DNA. The suitability of this peptide was then evaluated using a chromatography system with the 16mer peptide immobilized to a customized monolith to purify plasmid DNA, obtaining preferential purification of supercoiled pUC19. The results demonstrate the applicability of peptide-monolith supports to scale up the purification process for plasmid DNA using designed ligands via a biomimetic approach.

Versatility of polymethacrylate monoliths for chromatographic purification of biomolecules

Polymethacrylate monoliths, specifically poly(glycidyl methacrylate-co-ethylene dimethacrylate) or poly(GMA-co-EDMA) monoliths, are a new generation of chromatographic supports and are significantly different from conventional particle-based adsorbents, membranes, and other monolithic supports for biomolecule purification. Similar to other monoliths, polymethacrylate monoliths possess large pores which allow convective flow of mobile phase and result in high flow rates at reduced pressure drop, unlike particulate supports. The simplicity of the adsorbent synthesis, pH resistance, and the ease and flexibility of tailoring their pore size to that of the target biomolecule are the key properties which differentiate polymethacrylate monoliths from other monoliths. Polymethacrylate monoliths are endowed with reactive epoxy groups for easy functionalization (with anion-exchange, hydrophobic, and affinity ligands) and high ligand retention. In this review, the structure and performance of polymethacrylate monoliths for chromatographic purification of biomolecules are evaluated and compared to those of other supports. The development and use of polymethacrylate monoliths for research applications have grown rapidly in recent times and have enabled the achievement of high through-put biomolecule purification on semi-preparative and preparative scales.

A thermal expulsion approach to homogeneous large-volume methacrylate monolith preparation; enabling large-scale rapid purification of biomolecules

Numerous efforts have been dedicated to the synthesis of large-volume methacrylate monoliths for large-scale biomolecules purification but most were obstructed by the enormous release of exotherms during preparation, thereby introducing structural heterogeneity in the monolith pore system. A significant radial temperature gradient develops along the monolith thickness, reaching a terminal temperature that supersedes the maximum temperature required for structurally homogenous monoliths preparation. The enormous heat build-up is perceived to encompass the heat associated with initiator decomposition and the heat released from free radical-monomer and monomer-monomer interactions. The heat resulting from the initiator decomposition was expelled along with some gaseous fumes before commencing polymerization in a gradual addition fashion. Characteristics of 80 mL monolith prepared using this technique was compared with that of a similar monolith synthesized in a bulk polymerization mode. An extra similarity in the radial temperature profiles was observed for the monolith synthesized via the heat expulsion technique. A maximum radial temperature gradient of only 4.3°C was recorded at the center and 2.1°C at the monolith peripheral for the combined heat expulsion and gradual addition technique. The comparable radial temperature distributions obtained birthed identical pore size distributions at different radial points along the monolith thickness.

Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator

We report a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form using digitally reconfigurable ring oscillator (RO). Solving a system of linear equations with different configuration setting of the RO gives delay of an individual gate. Experimental results from a test chip in 65nm process node show the feasibility of measuring the delay of an individual inverter to within 1pS accuracy. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 26% indicating the large impact of local or within-die variations.

Novel CMOS Schmitt trigger

A novel CMOS Schmitt trigger using only four MOS transistors is discussed. This circuit, which works on the principle of load-coupled regenerative feedback, can be implemented using conventional CMOS technology with only one extra fabrication step. It can be implemented even more easily in CMOS/SOS (silicon-on-sapphire) integrated circuits. The hysteresis of this Schmitt trigger can be controlled by a proper choice of the transistor geometries.

Linear transconductor with flipped voltage follower in 130 nm CMOS

This paper presents a modified design method for linear transconductor circuit in 130 nm CMOS technology to improve linearity, robustness against process induced threshold voltage variability and reduce harmonic distortion. Source follower in the adaptively biased differential pair (ABDP) linear transconductor circuit is replaced with flipped voltage follower to improve the efficiency of the tail current source, which is connected to a conventional differential pair. The simulation results show the performance of the modified circuit also has better speed, noise performance and common mode rejection ratio compared to the ABDP circuit.

Reliability analysis of torsional varactor

A torsional MEMS varactor with wide dynamic range, lower actuation voltage and isolation between actuation voltage and signal voltage has been proposed in C. Venkatesh et al. (2005). In this paper we address the effects of pull-in, residual stress and continuous cycling on the performance of torsional MEMS varactor.

Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks

Artificial neural networks (ANNs) have shown great promise in modeling circuit parameters for computer aided design applications. Leakage currents, which depend on process parameters, supply voltage and temperature can be modeled accurately with ANNs. However, the complex nature of the ANN model, with the standard sigmoidal activation functions, does not allow analytical expressions for its mean and variance. We propose the use of a new activation function that allows us to derive an analytical expression for the mean and a semi-analytical expression for the variance of the ANN-based leakage model. To the best of our knowledge this is the first result in this direction. Our neural network model also includes the voltage and temperature as input parameters, thereby enabling voltage and temperature aware statistical leakage analysis (SLA). All existing SLA frameworks are closely tied to the exponential polynomial leakage model and hence fail to work with sophisticated ANN models. In this paper, we also set up an SLA framework that can efficiently work with these ANN models. Results show that the cumulative distribution function of leakage current of ISCAS'85 circuits can be predicted accurately with the error in mean and standard deviation, compared to Monte Carlo-based simulations, being less than 1% and 2% respectively across a range of voltage and temperature values.

SEU Tolerant Robust Memory Cell Design

The implementation of semiconductor circuits and systems in nano-technology makes it possible to achieve high speed, lower voltage level and smaller area. The unintended and undesirable result of this scaling is that it makes integrated circuits susceptible to soft errors normally caused by alpha particle or neutron hits. These events of radiation strike resulting into bit upsets referred to as single event upsets(SEU), become increasingly of concern for the reliable circuit operation in the field. Storage elements are worst hit by this phenomenon. As we further scale down, there is greater interest in reliability of the circuits and systems, apart from the performance, power and area aspects. In this paper we propose an improved 12T SEU tolerant SRAM cell design. The proposed SRAM cell is economical in terms of area overhead. It is easy to fabricate as compared to earlier designs. Simulation results show that the proposed cell is highly robust, as it does not flip even for a transient pulse with 62 times the Q(crit) of a standard 6T SRAM cell.

A 0.5-2.0 GHz injection locked oscillator cascade for parallel wideband RF spectrum sensing

An area-efficient, wideband RF frequency synthesizer, which simultaneously generates multiple local oscillator (LO) signals, is designed. It is suitable for parallel wideband RF spectrum sensing in cognitive radios. The frequency synthesizer consists of an injection locked oscillator cascade (ILOC) where all the LO signals are derived from a single reference oscillator. The ILOC is implemented in a 130-nm technology with an active area of . It generates 4 uniformly spaced LO carrier frequencies from 500 MHz to 2 GHz. This design is the first known implementation of a CMOS based ILOC for wide-band RF spectrum sensing applications.

A Mitigation Technique for Harmonic Downconversion in Wideband Spectrum Sensors

The down conversion of radio frequency components around the harmonics of the local oscillator (LO), and its impact on the accuracy of white space detection using integrated spectrum sensors, is studied. We propose an algorithm to mitigate the impact of harmonic downconversion by utilizing multiple parallel downconverters in the system architecture. The proposed algorithm is validated on a test-board using commercially available integrated circuits and a test-chip implemented in a 130-nm CMOS technology. The measured data show that the impact of the harmonic downconversion is closely related to the LO characteristics, and that much of it can be mitigated by the proposed technique.

Growth of ultrahigh density vertically aligned carbon nanotube forests for interconnects.

We present a general catalyst design to synthesize ultrahigh density, aligned forests of carbon nanotubes by cyclic deposition and annealing of catalyst thin films. This leads to nanotube forests with an area density of at least 10(13) cm(-2), over 1 order of magnitude higher than existing values, and close to the limit of a fully dense forest. The technique consists of cycles of ultrathin metal film deposition, annealing, and immobilization. These ultradense forests are needed to use carbon nanotubes as vias and interconnects in integrated circuits and thermal interface materials. Further density increase to 10(14) cm(-2) by reducing nanotube diameter is possible, and it is also applicable to nanowires.

Avances en algoritmos de estimación de distribuciones. Alternativas en el aprendizaje y representación de problemas

131 p.: graf.