In-situ detection of defect formation in organic flexible electronics by Kelvin Probe Force Microscopy

Organic semiconductor technology has attracted considerable research interest in view of its great promise for large area, lightweight, and flexible electronics applications. Owing to their advantages in processing and unique physical properties, organic semiconductors can bring exciting new opportunities for broad-impact applications requiring large area coverage, mechanical flexibility, low-temperature processing, and low cost. In order to achieve highly flexible device architecture it is crucial to understand on a microscopic scale how mechanical deformation affects the electrical performance of organic thin film devices. Towards this aim, I established in this thesis the experimental technique of Kelvin Probe Force Microscopy (KPFM) as a tool to investigate the morphology and the surface potential of organic semiconducting thin films under mechanical strain. KPFM has been employed to investigate the strain response of two different Organic Thin Film Transistor with active layer made by 6,13-bis(triisopropylsilylethynyl)-pentacene (TIPS-Pentacene), and Poly(3-hexylthiophene-2,5-diyl) (P3HT). The results show that this technique allows to investigate on a microscopic scale failure of flexible TFT with this kind of materials during bending. I find that the abrupt reduction of TIPS-pentacene device performance at critical bending radii is related to the formation of nano-cracks in the microcrystal morphology, easily identified due to the abrupt variation in surface potential caused by local increase in resistance. Numerical simulation of the bending mechanics of the transistor structure further identifies the mechanical strain exerted on the TIPS-pentacene micro-crystals as the fundamental origin of fracture. Instead for P3HT based transistors no significant reduction in electrical performance is observed during bending. This finding is attributed to the amorphous nature of the polymer giving rise to an elastic response without the occurrence of crack formation.

Two-year follow-up of patients undergoing transcatheter aortic valve implantation using a self-expanding valve prosthesis

The purpose of this study was to evaluate the safety, device performance, and clinical outcome up to 2 years for patients undergoing transcatheter aortic valve implantation (TAVI).

Six-month angiographic follow-up of the PAS-Port II clinical trial

BACKGROUND: The PAS-Port device (Cardica, Redwood City, CA) allows the rapid deployment of a clampless proximal anastomosis between a vein graft and the aorta. METHODS: Fifty-four patients awaiting elective coronary artery bypass graft surgery were enrolled. Outcome variables were intraoperative device performance, early and 6- month angiographic graft patency, and 12-month clinical follow-up. RESULTS: Sixty-three PAS-Port devices were deployed in 54 patients. Two deployments were unsuccessful. There were no reoperations for bleeding. Two patients died of causes unrelated to the device. Patency evaluation at discharge was performed by angiogram on 49 implants and computed tomography in 2 implants (86% follow-up). At discharge, all evaluated grafts were patent (100%) and rated Fitzgibbon A. At 6-month follow-up, there was no additional mortality; 47 implants (88% follow-up) were evaluated by angiography (Fitzgibbon O [n = 1], Fitzgibbon B [n = 1], and Fitzgibbon A [n = 45]) and 5 by computed tomography. All grafts but 1 were patent (98.1%). At 12 months, 2 additional patients died of causes unrelated to the PAS-Port implant. Forty-six of 50 alive patients (95.8%) were followed up without any reports of device-related major adverse cardiac events. CONCLUSIONS: Discharge (100%) and 6-month patency (98%) are excellent; patency and 12 months' clinical follow-up compares favorably with data from historical hand-sewn controls. The PAS-Port system safely allows the clampless creation of a proximal anastomosis.

Contribución a los modelos de gestión de las redes móviles ad hoc

La capacidad de comunicación de los seres humanos ha crecido gracias a la evolución de dispositivos móviles cada vez más pequeños, manejables, potentes, de mayor autonomía y más asequibles. Esta tendencia muestra que en un futuro próximo cercano cada persona llevaría consigo por lo menos un dispositivo de altas prestaciones. Estos dispositivos tienen incorporados algunas formas de comunicación: red de telefonía, redes inalámbricas, bluetooth, entre otras. Lo que les permite también ser empleados para la configuración de redes móviles Ad Hoc. Las redes móviles Ad Hoc, son redes temporales y autoconfigurables, no necesitan un punto de acceso para que los nodos intercambien información entre sí. Cada nodo realiza las tareas de encaminador cuando sea requerido. Los nodos se pueden mover, cambiando de ubicación a discreción. La autonomía de estos dispositivos depende de las estrategias de como sus recursos son utilizados. De tal forma que los protocolos, algoritmos o modelos deben ser diseñados de forma eficiente para no impactar el rendimiento del dispositivo, siempre buscando un equilibrio entre sobrecarga y usabilidad. Es importante definir una gestión adecuada de estas redes especialmente cuando estén siendo utilizados en escenarios críticos como los de emergencias, desastres naturales, conflictos bélicos. La presente tesis doctoral muestra una solución eficiente para la gestión de redes móviles Ad Hoc. La solución contempla dos componentes principales: la definición de un modelo de gestión para redes móviles de alta disponibilidad y la creación de un protocolo de enrutamiento jerárquico asociado al modelo. El modelo de gestión propuesto, denominado High Availability Management Ad Hoc Network (HAMAN), es definido en una estructura de cuatro niveles, acceso, distribución, inteligencia e infraestructura. Además se describen los componentes de cada nivel: tipos de nodos, protocolos y funcionamiento. Se estudian también las interfaces de comunicación entre cada componente y la relación de estas con los niveles definidos. Como parte del modelo se diseña el protocolo de enrutamiento Ad Hoc, denominado Backup Cluster Head Protocol (BCHP), que utiliza como estrategia de encaminamiento el empleo de cluster y jerarquías. Cada cluster tiene un Jefe de Cluster que concentra la información de enrutamiento y de gestión y la envía al destino cuando esta fuera de su área de cobertura. Para mejorar la disponibilidad de la red el protocolo utiliza un Jefe de Cluster de Respaldo el que asume las funciones del nodo principal del cluster cuando este tiene un problema. El modelo HAMAN es validado a través de un proceso la simulación del protocolo BCHP. El protocolo BCHP se implementa en la herramienta Network Simulator 2 (NS2) para ser simulado, comparado y contrastado con el protocolo de enrutamiento jerárquico Cluster Based Routing Protocol (CBRP) y con el protocolo de enrutamiento Ad Hoc reactivo denominado Ad Hoc On Demand Distance Vector Routing (AODV). Abstract The communication skills of humans has grown thanks to the evolution of mobile devices become smaller, manageable, powerful, more autonomy and more affordable. This trend shows that in the near future each person will carry at least one high-performance device. These high-performance devices have some forms of communication incorporated: telephony network, wireless networks, bluetooth, among others. What can also be used for configuring mobile Ad Hoc networks. Ad Hoc mobile networks, are temporary and self-configuring networks, do not need an access point for exchange information between their nodes. Each node performs the router tasks as required. The nodes can move, change location at will. The autonomy of these devices depends on the strategies of how its resources are used. So that the protocols, algorithms or models should be designed to efficiently without impacting device performance seeking a balance between overhead and usability. It is important to define appropriate management of these networks, especially when being used in critical scenarios such as emergencies, natural disasters, wars. The present research shows an efficient solution for managing mobile ad hoc networks. The solution comprises two main components: the definition of a management model for highly available mobile networks and the creation of a hierarchical routing protocol associated with the model. The proposed management model, called High Availability Management Ad Hoc Network (HAMAN) is defined in a four-level structure: access, distribution, intelligence and infrastructure. The components of each level: types of nodes, protocols, structure of a node are shown and detailed. It also explores the communication interfaces between each component and the relationship of these with the levels defined. The Ad Hoc routing protocol proposed, called Backup Cluster Head Protocol( BCHP), use of cluster and hierarchies like strategies. Each cluster has a cluster head which concentrates the routing information and management and sent to the destination when out of cluster coverage area. To improve the availability of the network protocol uses a Backup Cluster Head who assumes the functions of the node of the cluster when it has a problem. The HAMAN model is validated accross the simulation of their BCHP routing protocol. BCHP protocol has been implemented in the simulation tool Network Simulator 2 (NS2) to be simulated, compared and contrasted with a hierarchical routing protocol Cluster Based Routing Protocol (CBRP) and a routing protocol called Reactive Ad Hoc On Demand Distance Vector Routing (AODV).

TCAD for PV: a fast method for accurately modelling metal impurity evolution during solar cell processing

Coupled device and process silumation tools, collectively known as technology computer-aided design (TCAD), have been used in the integrated circuit industry for over 30 years. These tools allow researchers to quickly converge on optimized devide designs and manufacturing processes with minimal experimental expenditures. The PV industry has been slower to adopt these tools, but is quickly developing competency in using them. This paper introduces a predictive defect engineering paradigm and simulation tool, while demonstrating its effectiveness at increasing the performance and throughput of current industrial processes. the impurity-to-efficiency (I2E) simulator is a coupled process and device simulation tool that links wafer material purity, processing parameters and cell desigh to device performance. The tool has been validated with experimental data and used successfully with partners in industry. The simulator has also been deployed in a free web-accessible applet, which is available for use by the industrial and academic communities.

Optimization of AlN thin layers on diamond substrates for high frequency SAW resonators

AlN/diamond heterostructures are very promising for high frequency surface acoustic wave (SAW) resonators. In their design, the thickness of the piezoelectric film is one of the key parameters. On the other hand, the film material quality and, hence, the device performance, also depend on that thickness. In this work, polished microcrystalline diamond substrates have been used to deposit AlN films by reactive sputtering, from 150 nm up to 3 μm thick. A high degree of the c-axis orientation has been obtained in all cases. SAW one port resonators at high frequency have been fabricated on these films with a proper combination of the film thickness and transducer size.

Technology and characterization of GaN-HEMTs devices: high temperature and trapping effects

Los transistores de alta movilidad electrónica basados en GaN han sido objeto de una extensa investigación ya que tanto el GaN como sus aleaciones presentan unas excelentes propiedades eléctricas (alta movilidad, elevada concentración de portadores y campo eléctrico crítico alto). Aunque recientemente se han incluido en algunas aplicaciones comerciales, su expansión en el mercado está condicionada a la mejora de varios asuntos relacionados con su rendimiento y habilidad. Durante esta tesis se han abordado algunos de estos aspectos relevantes; por ejemplo, la fabricación de enhancement mode HEMTs, su funcionamiento a alta temperatura, el auto calentamiento y el atrapamiento de carga. Los HEMTs normalmente apagado o enhancement mode han atraído la atención de la comunidad científica dedicada al desarrollo de circuitos amplificadores y conmutadores de potencia, ya que su utilización disminuiría significativamente el consumo de potencia; además de requerir solamente una tensión de alimentación negativa, y reducir la complejidad del circuito y su coste. Durante esta tesis se han evaluado varias técnicas utilizadas para la fabricación de estos dispositivos: el ataque húmedo para conseguir el gate-recess en heterostructuras de InAl(Ga)N/GaN; y tratamientos basados en flúor (plasma CF4 e implantación de F) de la zona debajo de la puerta. Se han llevado a cabo ataques húmedos en heteroestructuras de InAl(Ga)N crecidas sobre sustratos de Si, SiC y zafiro. El ataque completo de la barrera se consiguió únicamente en las muestras con sustrato de Si. Por lo tanto, se puede deducir que la velocidad de ataque depende de la densidad de dislocaciones presentes en la estructura, ya que el Si presenta un peor ajuste del parámetro de red con el GaN. En relación a los tratamientos basados en flúor, se ha comprobado que es necesario realizar un recocido térmico después de la fabricación de la puerta para recuperar la heteroestructura de los daños causados durante dichos tratamientos. Además, el estudio de la evolución de la tensión umbral con el tiempo de recocido ha demostrado que en los HEMTs tratados con plasma ésta tiende a valores más negativos al aumentar el tiempo de recocido. Por el contrario, la tensión umbral de los HEMTs implantados se desplaza hacia valores más positivos, lo cual se atribuye a la introducción de iones de flúor a niveles más profundos de la heterostructura. Los transistores fabricados con plasma presentaron mejor funcionamiento en DC a temperatura ambiente que los implantados. Su estudio a alta temperatura ha revelado una reducción del funcionamiento de todos los dispositivos con la temperatura. Los valores iniciales de corriente de drenador y de transconductancia medidos a temperatura ambiente se recuperaron después del ciclo térmico, por lo que se deduce que dichos efectos térmicos son reversibles. Se han estudiado varios aspectos relacionados con el funcionamiento de los HEMTs a diferentes temperaturas. En primer lugar, se han evaluado las prestaciones de dispositivos de AlGaN/GaN sobre sustrato de Si con diferentes caps: GaN, in situ SiN e in situ SiN/GaN, desde 25 K hasta 550 K. Los transistores con in situ SiN presentaron los valores más altos de corriente drenador, transconductancia, y los valores más bajos de resistencia-ON, así como las mejores características en corte. Además, se ha confirmado que dichos dispositivos presentan gran robustez frente al estrés térmico. En segundo lugar, se ha estudiado el funcionamiento de transistores de InAlN/GaN con diferentes diseños y geometrías. Dichos dispositivos presentaron una reducción casi lineal de los parámetros en DC en el rango de temperaturas de 25°C hasta 225°C. Esto se debe principalmente a la dependencia térmica de la movilidad electrónica, y también a la reducción de la drift velocity con la temperatura. Además, los transistores con mayores longitudes de puerta mostraron una mayor reducción de su funcionamiento, lo cual se atribuye a que la drift velocity disminuye más considerablemente con la temperatura cuando el campo eléctrico es pequeño. De manera similar, al aumentar la distancia entre la puerta y el drenador, el funcionamiento del HEMT presentó una mayor reducción con la temperatura. Por lo tanto, se puede deducir que la degradación del funcionamiento de los HEMTs causada por el aumento de la temperatura depende tanto de la longitud de la puerta como de la distancia entre la puerta y el drenador. Por otra parte, la alta densidad de potencia generada en la región activa de estos transistores conlleva el auto calentamiento de los mismos por efecto Joule, lo cual puede degradar su funcionamiento y Habilidad. Durante esta tesis se ha desarrollado un simple método para la determinación de la temperatura del canal basado en medidas eléctricas. La aplicación de dicha técnica junto con la realización de simulaciones electrotérmicas han posibilitado el estudio de varios aspectos relacionados con el autocalentamiento. Por ejemplo, se han evaluado sus efectos en dispositivos sobre Si, SiC, y zafiro. Los transistores sobre SiC han mostrado menores efectos gracias a la mayor conductividad térmica del SiC, lo cual confirma el papel clave que desempeña el sustrato en el autocalentamiento. Se ha observado que la geometría del dispositivo tiene cierta influencia en dichos efectos, destacando que la distribución del calor generado en la zona del canal depende de la distancia entre la puerta y el drenador. Además, se ha demostrado que la temperatura ambiente tiene un considerable impacto en el autocalentamiento, lo que se atribuye principalmente a la dependencia térmica de la conductividad térmica de las capas y sustrato que forman la heterostructura. Por último, se han realizado numerosas medidas en pulsado para estudiar el atrapamiento de carga en HEMTs sobre sustratos de SiC con barreras de AlGaN y de InAlN. Los resultados obtenidos en los transistores con barrera de AlGaN han presentado una disminución de la corriente de drenador y de la transconductancia sin mostrar un cambio en la tensión umbral. Por lo tanto, se puede deducir que la posible localización de las trampas es la región de acceso entre la puerta y el drenador. Por el contrario, la reducción de la corriente de drenador observada en los dispositivos con barrera de InAlN llevaba asociado un cambio significativo en la tensión umbral, lo que implica la existencia de trampas situadas en la zona debajo de la puerta. Además, el significativo aumento del valor de la resistencia-ON y la degradación de la transconductancia revelan la presencia de trampas en la zona de acceso entre la puerta y el drenador. La evaluación de los efectos del atrapamiento de carga en dispositivos con diferentes geometrías ha demostrado que dichos efectos son menos notables en aquellos transistores con mayor longitud de puerta o mayor distancia entre puerta y drenador. Esta dependencia con la geometría se puede explicar considerando que la longitud y densidad de trampas de la puerta virtual son independientes de las dimensiones del dispositivo. Finalmente se puede deducir que para conseguir el diseño óptimo durante la fase de diseño no sólo hay que tener en cuenta la aplicación final sino también la influencia que tiene la geometría en los diferentes aspectos estudiados (funcionamiento a alta temperatura, autocalentamiento, y atrapamiento de carga). ABSTRACT GaN-based high electron mobility transistors have been under extensive research due to the excellent electrical properties of GaN and its related alloys (high carrier concentration, high mobility, and high critical electric field). Although these devices have been recently included in commercial applications, some performance and reliability issues need to be addressed for their expansion in the market. Some of these relevant aspects have been studied during this thesis; for instance, the fabrication of enhancement mode HEMTs, the device performance at high temperature, the self-heating and the charge trapping. Enhancement mode HEMTs have become more attractive mainly because their use leads to a significant reduction of the power consumption during the stand-by state. Moreover, they enable the fabrication of simpler power amplifier circuits and high-power switches because they allow the elimination of negativepolarity voltage supply, reducing significantly the circuit complexity and system cost. In this thesis, different techniques for the fabrication of these devices have been assessed: wet-etching for achieving the gate-recess in InAl(Ga)N/GaN devices and two different fluorine-based treatments (CF4 plasma and F implantation). Regarding the wet-etching, experiments have been carried out in InAl(Ga)N/GaN grown on different substrates: Si, sapphire, and SiC. The total recess of the barrier was achieved after 3 min of etching in devices grown on Si substrate. This suggests that the etch rate can critically depend on the dislocations present in the structure, since the Si exhibits the highest mismatch to GaN. Concerning the fluorine-based treatments, a post-gate thermal annealing was required to recover the damages caused to the structure during the fluorine-treatments. The study of the threshold voltage as a function of this annealing time has revealed that in the case of the plasma-treated devices it become more negative with the time increase. On the contrary, the threshold voltage of implanted HEMTs showed a positive shift when the annealing time was increased, which is attributed to the deep F implantation profile. Plasma-treated HEMTs have exhibited better DC performance at room temperature than the implanted devices. Their study at high temperature has revealed that their performance decreases with temperature. The initial performance measured at room temperature was recovered after the thermal cycle regardless of the fluorine treatment; therefore, the thermal effects were reversible. Thermal issues related to the device performance at different temperature have been addressed. Firstly, AlGaN/GaN HEMTs grown on Si substrate with different cap layers: GaN, in situ SiN, or in situ SiN/GaN, have been assessed from 25 K to 550 K. In situ SiN cap layer has been demonstrated to improve the device performance since HEMTs with this cap layer have exhibited the highest drain current and transconductance values, the lowest on-resistance, as well as the best off-state characteristics. Moreover, the evaluation of thermal stress impact on the device performance has confirmed the robustness of devices with in situ cap. Secondly, the high temperature performance of InAlN/GaN HEMTs with different layouts and geometries have been assessed. The devices under study have exhibited an almost linear reduction of the main DC parameters operating in a temperature range from room temperature to 225°C. This was mainly due to the thermal dependence of the electron mobility, and secondly to the drift velocity decrease with temperature. Moreover, HEMTs with large gate length values have exhibited a great reduction of the device performance. This was attributed to the greater decrease of the drift velocity for low electric fields. Similarly, the increase of the gate-to-drain distance led to a greater reduction of drain current and transconductance values. Therefore, this thermal performance degradation has been found to be dependent on both the gate length and the gate-to-drain distance. It was observed that the very high power density in the active region of these transistors leads to Joule self-heating, resulting in an increase of the device temperature, which can degrade the device performance and reliability. A simple electrical method have been developed during this work to determine the channel temperature. Furthermore, the application of this technique together with the performance of electro-thermal simulations have enabled the evaluation of different aspects related to the self-heating. For instance, the influence of the substrate have been confirmed by the study of devices grown on Si, SiC, and Sapphire. HEMTs grown on SiC substrate have been confirmed to exhibit the lowest self-heating effects thanks to its highest thermal conductivity. In addition to this, the distribution of the generated heat in the channel has been demonstrated to be dependent on the gate-to-drain distance. Besides the substrate and the geometry of the device, the ambient temperature has also been found to be relevant for the self-heating effects, mainly due to the temperature-dependent thermal conductivity of the layers and the substrate. Trapping effects have been evaluated by means of pulsed measurements in AlGaN and InAIN barrier devices. AlGaN barrier HEMTs have exhibited a de crease in drain current and transconductance without measurable threshold voltage change, suggesting the location of the traps in the gate-to-drain access region. On the contrary, InAIN barrier devices have showed a drain current associated with a positive shift of threshold voltage, which indicated that the traps were possibly located under the gate region. Moreover, a significant increase of the ON-resistance as well as a transconductance reduction were observed, revealing the presence of traps on the gate-drain access region. On the other hand, the assessment of devices with different geometries have demonstrated that the trapping effects are more noticeable in devices with either short gate length or the gate-to-drain distance. This can be attributed to the fact that the length and the trap density of the virtual gate are independent on the device geometry. Finally, it can be deduced that besides the final application requirements, the influence of the device geometry on the performance at high temperature, on the self-heating, as well as on the trapping effects need to be taken into account during the device design stage to achieve the optimal layout.

Improving the pass-band return loss in liquid crystal dual-mode bandpass filters by microstrip patch reshaping

In this paper, the design and experimental characterization of a tunable microstrip bandpass filter based on liquid crystal technology are presented. A reshaped microstrip dual-mode filter structure has been used in order to improve the device performance. Specifically, the aim is to increase the pass-band return loss of the filter by narrowing the filter bandwidth. Simulations confirm the improvement of using this new structure, achieving a pass-band return loss increase of 1.5 dB at least. Because of the anisotropic properties of LC molecules, a filter central frequency shift from 4.688 GHz to 5.045 GHz, which means a relative tuning range of 7.3%, is measured when an external AC voltage from 0 Vrms to 15 Vrms is applied to the device.

Design, Technology and Characterization of Micromechanised Sensors and Actuators for Harsh Environments

Los sistemas micro electro mecánicos (MEMS) han demostrado ser una exitosa familia de dispositivos que pueden usarse como plataforma para el desarrollo de dispositivos con aplicaciones en óptica, comunicaciones, procesado de señal y sensorización. Los dispositivos MEMS estándar suelen estar fabricados usando tecnología de silicio. Sin embargo, el rendimiento de estos MEMS se puede mejorar si se usan otros materiales. Por ejemplo, el diamante nanocristalino (NCD) ofrece unas excelentes propiedades mecánicas, transparencia y una superficie fácil de funcionalizar. Por otro lado, el sistema de materiales (In; Ga; Al)N, los materiales IIIN, se pueden usar para producir estructuras monocristalinas con alta sensibilidad mecánica y química. Además, el AlN se puede depositar por pulverización catódica reactiva sobre varios substratos, incluyendo NCD, para formar capas policristalinas orientadas con alta respuesta piezoeléctrica. Adicionalmente, tanto el NCD como los materiales III-N muestran una gran estabilidad térmica y química, lo que los hace una elección idónea para desarrollar dispositivos para aplicaciones para alta temperatura, ambientes agresivos e incluso para aplicaciones biocompatibles. En esta tesis se han usado estos materiales para el diseño y medición de demostradores tecnológicos. Se han perseguido tres objetivos principales: _ Desarrollo de unos procesos de fabricación apropiados. _ Medición de las propiedades mecánicas de los materiales y de los factores que limitan el rendimiento de los dispositivos. _ Usar los datos medidos para desarrollar dispositivos demostradores complejos. En la primera parte de esta tesis se han estudiado varias técnicas de fabricación. La estabilidad de estos materiales impide el ataque y dificulta la producción de estructuras suspendidas. Los primeros capítulos de esta disertación se dedican al desarrollo de unos procesos de transferencia de patrones por ataque seco y a la optimización del ataque húmedo sacrificial de varios substratos propuestos. Los resultados de los procedimientos de ataque se presentan y se describe la optimización de las técnicas para la fabricación de estructuras suspendidas de NCD y materiales III-N. En un capítulo posterior se estudia el crecimiento de AlN por pulverización catódica. Como se ha calculado en esta disertación para obtener una actuación eficiente de MEMS, las capas de AlN han de ser finas, típicamente d < 200 nm, lo que supone serias dificultades para la obtención de capas orientadas con respuesta piezoeléctrica. Las condiciones de depósito se han mapeado para identificar las fronteras que proporcionan el crecimiento de material orientado desde los primeros pasos del proceso. Además, durante la optimización de los procesos de ataque se estudió un procedimiento para fabricar películas de GaN nanoporoso. Estas capas porosas pueden servir como capas sacrificiales para la fabricación de estructuras suspendidas de GaN con baja tensión residual o como capas para mejorar la funcionalización superficial de sensores químicos o biológicos. El proceso de inducción de poros se discutirá y también se presentarán experimentos de ataque y funcionalización. En segundo lugar, se han determinado las propiedades mecánicas del NCD y de los materiales III-N. Se han fabricado varias estructuras suspendidas para la medición del módulo de Young y de la tensión residual. Además, las estructuras de NCD se midieron en resonancia para calcular el rendimiento de los dispositivos en términos de frecuencia y factor de calidad. Se identificaron los factores intrínsecos y extrínsecos que limitan ambas figuras de mérito y se han desarrollado modelos para considerar estas imperfecciones en las etapas de diseño de los dispositivos. Por otra parte, los materiales III-N normalmente presentan grandes gradientes de deformación residual que causan la deformación de las estructuras al ser liberadas. Se han medido y modelado estos efectos para los tres materiales binarios del sistema para proporcionar puntos de interpolación que permitan predecir las características de las aleaciones del sistema III-N. Por último, los datos recabados se han usado para desarrollar modelos analíticos y numéricos para el diseño de varios dispositivos. Se han estudiado las propiedades de transducción y se proporcionan topologías optimizadas. En el último capítulo de esta disertación se presentan diseños optimizados de los siguientes dispositivos: _ Traviesas y voladizos de AlN=NCD con actuación piezoeléctrica aplicados a nanoconmutadores de RF para señales de alta potencia. _ Membranas circulares de AlN=NCD con actuación piezoeléctrica aplicadas a lentes sintonizables. _ Filtros ópticos Fabry-Pérot basados en cavidades aéreas y membranas de GaN actuadas electrostáticamente. En resumen, se han desarrollado unos nuevos procedimientos optimizados para la fabricación de estructuras de NCD y materiales III-N. Estas técnicas se han usado para producir estructuras que llevaron a la determinación de las principales propiedades mecánicas y de los parámetros de los dispositivos necesarios para el diseño de MEMS. Finalmente, los datos obtenidos se han usado para el diseño optimizado de varios dispositivos demostradores. ABSTRACT Micro Electro Mechanical Systems (MEMS) have proven to be a successful family of devices that can be used as a platform for the development of devices with applications in optics, communications, signal processing and sensorics. Standard MEMS devices are usually fabricated using silicon based materials. However, the performance of these MEMS can be improved if other material systems are used. For instance, nanocrystalline diamond (NCD) offers excellent mechanical properties, optical transparency and ease of surface functionalization. On the other hand, the (In; Ga; Al)N material system, the III-N materials, can be used to produce single crystal structures with high mechanical and chemical sensitivity. Also, AlN can be deposited by reactive sputtering on various substrates, including NCD, to form oriented polycrystalline layers with high piezoelectric response. In addition, both NCD and III-N materials exhibit high thermal and chemical stability, which makes these material the perfect choice for the development of devices for high temperatures, harsh environments and even biocompatible applications. In this thesis these materials have been used for the design and measurement of technological demonstrators. Three main objectives have been pursued: _ Development of suitable fabrication processes. _ Measurement of the material mechanical properties and device performance limiting factors. _ Use the gathered data to design complex demonstrator devices. In a first part of the thesis several fabrication processes have been addressed. The stability of these materials hinders the etching of the layers and hampers the production of free standing structures. The first chapters of this dissertation are devoted to the development of a dry patterning etching process and to sacrificial etching optimization of several proposed substrates. The results of the etching processes are presented and the optimization of the technique for the manufacturing of NCD and III-N free standing structures is described. In a later chapter, sputtering growth of thin AlN layers is studied. As calculated in this dissertation, for efficient MEMS piezoelectric actuation the AlN layers have to be very thin, typically d < 200 nm, which poses serious difficulties to the production of c-axis oriented material with piezoelectric response. The deposition conditions have been mapped in order to identify the boundaries that give rise to the growth of c-axis oriented material from the first deposition stages. Additionally, during the etching optimization a procedure for fabricating nanoporous GaN layers was also studied. Such porous layers can serve as a sacrificial layer for the release of low stressed GaN devices or as a functionalization enhancement layer for chemical and biological sensors. The pore induction process will be discussed and etching and functionalization trials are presented. Secondly, the mechanical properties of NCD and III-N materials have been determined. Several free standing structures were fabricated for the measurement of the material Young’s modulus and residual stress. In addition, NCD structures were measured under resonance in order to calculate the device performance in terms of frequency and quality factor. Intrinsic and extrinsic limiting factors for both figures were identified and models have been developed in order to take into account these imperfections in the device design stages. On the other hand, III-N materials usually present large strain gradients that lead to device deformation after release. These effects have been measured and modeled for the three binary materials of the system in order to provide the interpolation points for predicting the behavior of the III-N alloys. Finally, the gathered data has been used for developing analytic and numeric models for the design of various devices. The transduction properties are studied and optimized topologies are provided. Optimized design of the following devices is presented at the last chapter of this dissertation: _ AlN=NCD piezoelectrically actuated beams applied to RF nanoswitches for large power signals. _ AlN=NCD piezoelectrically actuated circular membranes applied to tunable lenses. _ GaN based air gap tunable optical Fabry-Pérot filters with electrostatic actuation. On the whole, new optimized fabrication processes has been developed for the fabrication of NCD and III-N MEMS structures. These processing techniques was used to produce structures that led to the determination of the main mechanical properties and device parameters needed for MEMS design. Lastly, the gathered data was used for the design of various optimized demonstrator devices.

Oxide Semiconductors For Organic Opto-electronic Devices

Development of transparent oxide semiconductors (TOS) from Earth-abundant materials is of great interest for cost-effective thin film device applications, such as solar cells, light emitting diodes (LEDs), touch-sensitive displays, electronic paper, and transparent thin film transistors. The need of inexpensive or high performance electrode might be even greater for organic photovoltaic (OPV), with the goal to harvest renewable energy with inexpensive, lightweight, and cost competitive materials. The natural abundance of zinc and the wide bandgap ($sim$3.3 eV) of its oxide make it an ideal candidate. In this dissertation, I have introduced various concepts on the modulations of various surface, interface and bulk opto-electronic properties of ZnO based semiconductor for charge transport, charge selectivity and optimal device performance. I have categorized transparent semiconductors into two sub groups depending upon their role in a device. Electrodes, usually 200 to 500 nm thick, optimized for good transparency and transporting the charges to the external circuit. Here, the electrical conductivity in parallel direction to thin film, i.e bulk conductivity is important. And contacts, usually 5 to 50 nm thick, are optimized in case of solar cells for providing charge selectivity and asymmetry to manipulate the built in field inside the device for charge separation and collection. Whereas in Organic LEDs (OLEDs), contacts provide optimum energy level alignment at organic oxide interface for improved charge injections. For an optimal solar cell performance, transparent electrodes are designed with maximum transparency in the region of interest to maximize the light to pass through to the absorber layer for photo-generation, plus they are designed for minimum sheet resistance for efficient charge collection and transport. As such there is need for material with high conductivity and transparency. Doping ZnO with some common elements such as B, Al, Ga, In, Ge, Si, and F result in n-type doping with increase in carriers resulting in high conductivity electrode, with better or comparable opto-electronic properties compared to current industry-standard indium tin oxide (ITO). Furthermore, improvement in mobility due to improvement on crystallographic structure also provide alternative path for high conductivity ZnO TCOs. Implementing these two aspects, various studies were done on gallium doped zinc oxide (GZO) transparent electrode, a very promising indium free electrode. The dynamics of the superimposed RF and DC power sputtering was utilized to improve the microstructure during the thin films growth, resulting in GZO electrode with conductivity greater than 4000 S/cm and transparency greater than 90 %. Similarly, various studies on research and development of Indium Zinc Tin Oxide and Indium Zinc Oxide thin films which can be applied to flexible substrates for next generation solar cells application is presented. In these new TCO systems, understanding the role of crystallographic structure ranging from poly-crystalline to amorphous phase and the influence on the charge transport and optical transparency as well as important surface passivation and surface charge transport properties. Implementation of these electrode based on ZnO on opto-electronics devices such as OLED and OPV is complicated due to chemical interaction over time with the organic layer or with ambient. The problem of inefficient charge collection/injection due to poor understanding of interface and/or bulk property of oxide electrode exists at several oxide-organic interfaces. The surface conductivity, the work function, the formation of dipoles and the band-bending at the interfacial sites can positively or negatively impact the device performance. Detailed characterization of the surface composition both before and after various chemicals treatment of various oxide electrode can therefore provide insight into optimization of device performance. Some of the work related to controlling the interfacial chemistry associated with charge transport of transparent electrodes are discussed. Thus, the role of various pre-treatment on poly-crystalline GZO electrode and amorphous indium zinc oxide (IZO) electrode is compared and contrasted. From the study, we have found that removal of defects and self passivating defects caused by accumulation of hydroxides in the surface of both poly-crystalline GZO and amorphous IZO, are critical for improving the surface conductivity and charge transport. Further insight on how these insulating and self-passivating defects cause charge accumulation and recombination in an device is discussed. With recent rapid development of bulk-heterojunction organic photovoltaics active materials, devices employing ZnO and ZnO based electrode provide air stable and cost-competitive alternatives to traditional inorganic photovoltaics. The organic light emitting diodes (OLEDs) have already been commercialized, thus to follow in the footsteps of this technology, OPV devices need further improvement in power conversion efficiency and stable materials resulting in long device lifetimes. Use of low work function metals such as Ca/Al in standard geometry do provide good electrode for electron collection, but serious problems using low work-function metal electrodes originates from the formation of non-conductive metal oxide due to oxidation resulting in rapid device failure. Hence, using low work-function, air stable, conductive metal oxides such as ZnO as electrons collecting electrode and high work-function, air stable metals such as silver for harvesting holes, has been on the rise. Devices with degenerately doped ZnO functioning as transparent conductive electrode, or as charge selective layer in a polymer/fullerene based heterojunction, present useful device structures for investigating the functional mechanisms within OPV devices and a possible pathway towards improved air-stable high efficiency devices. Furthermore, analysis of the physical properties of the ZnO layers with varying thickness, crystallographic structure, surface chemistry and grain size deposited via various techniques such as atomic layer deposition, sputtering and solution-processed ZnO with their respective OPV device performance is discussed. We find similarity and differences in electrode property for good charge injection in OLEDs and good charge collection in OPV devices very insightful in understanding physics behind device failures and successes. In general, self-passivating surface of amorphous TCOs IZO, ZTO and IZTO forms insulating layer that hinders the charge collection. Similarly, we find modulation of the carrier concentration and the mobility in electron transport layer, namely zinc oxide thin films, very important for optimizing device performance.

Estudo de transistores de tunelamento induzido por efeito de campo (TFET) construídos em nanofio.

Esse trabalho de mestrado teve como estudo o transistor Túnel-FET (TFET) fabricado em estrutura de nanofio de silício. Este estudo foi feito de forma teórica (simulação numérica) e experimental. Foram estudadas as principais características digitais e analógicas do dispositivo e seu potencial para uso em circuitos integrados avançados para a próxima década. A análise foi feita através da extração experimental e estudo dos principais parâmetros do dispositivo, tais como inclinação de sublimiar, transcondutância (gm), condutância de saída (gd), ganho intrínseco de tensão (AV) e eficiência do transistor. As medidas experimentais foram comparadas com os resultados obtidos pela simulação. Através do uso de diferentes parâmetros de ajuste e modelos de simulação, justificou-se o comportamento do dispositivo observado experimentalmente. Durante a execução deste trabalho estudou-se a influência da escolha do material de fonte no desempenho do dispositivo, bem como o impacto do diâmetro do nanofio nos principais parâmetros analógicos do transistor. Os dispositivos compostos por fonte de SiGe apresentaram valores maiores de gm e gd do que aqueles compostos por fonte de silício. A diferença percentual entre os valores de transcondutância para os diferentes materiais de fonte variou de 43% a 96%, sendo dependente do método utilizado para comparação, e a diferença percentual entre os valores de condutância de saída variou de 38% a 91%. Observou-se também uma degradação no valor de AV com a redução do diâmetro do nanofio. O ganho calculado a partir das medidas experimentais para o dispositivo com diâmetro de 50 nm é aproximadamente 45% menor do que o correspondente ao diâmetro de 110 nm. Adicionalmente estudou-se o impacto do diâmetro considerando diferentes polarizações de porta (VG) e concluiu-se que os TFETs apresentam melhor desempenho para baixos valores de VG (houve uma redução de aproximadamente 88% no valor de AV com o aumento da tensão de porta de 1,25 V para 1,9 V). A sobreposição entre porta e fonte e o perfil de dopantes na junção de tunelamento também foram analisados a fim de compreender qual combinação dessas características resultariam em um melhor desempenho do dispositivo. Observou-se que os melhores resultados estavam associados a um alinhamento entre o eletrodo de porta e a junção entre fonte e canal e a um perfil abrupto de dopantes na junção. Por fim comparou-se a tecnologia MOS com o TFET, obtendo-se como resultado um maior valor de AV (maior do que 40 dB) para o TFET.

Organic distributed feedback laser to monitor solvent extraction upon thermal annealing in solution-processed polymer films

Solution-processed polymer films are used in multiple technological applications. The presence of residual solvent in the film, as a consequence of the preparation method, affects the material properties, so films are typically subjected to post-deposition thermal annealing treatments aiming at its elimination. Monitoring the amount of solvent eliminated as a function of the annealing parameters is important to design a proper treatment to ensure complete solvent elimination, crucial to obtain reproducible and stable material properties and therefore, device performance. Here we demonstrate, for the first time to our knowledge, the use of an organic distributed feedback (DFB) laser to monitor with high precision the amount of solvent extracted from a spin-coated polymer film as a function of the thermal annealing time. The polymer film of interest, polystyrene in the present work, is doped with a small amount of a laser dye as to constitute the active layer of the laser device and deposited over a reusable DFB resonator. It is shown that solvent elimination translates into shifts in the DFB laser wavelength, as a consequence of changes in film thickness and refractive index. The proposed method is expected to be applicable to other types of annealing treatments, polymer-solvent combinations or film deposition methods, thus constituting a valuable tool to accurately control the quality and reproducibility of solution-processed polymer thin films.

Compact tunable microfluidic interferometer

We demonstrate a compact tunable filter based on a novel microfluidic single beam Mach-Zehnder interferometer. The optical path difference occurs during propagation across a fluid-air interface ( meniscus), the inherent mobility of which provides tunability. Optical losses are minimized by optimizing the meniscus shape through surface treatment. Optical spectra are compared to a 3D beam propagation method simulations and good agreement is found. Tunability, low insertion loss and strength of the resonance are well reproduced. The device performance displays a resonance depth of - 28 dB and insertion loss maintained at - 4 dB. (C) 2004 Optical Society of America.

Direct measurement of coherency limits for strain relaxation in heteroepitaxial core/shell nanowires

The growth of heteroepitaxially strained semiconductors at the nanoscale enables tailoring of material properties for enhanced device performance. For core/shell nanowires (NWs), theoretical predictions of the coherency limits and the implications they carry remain uncertain without proper identification of the mechanisms by which strains relax. We present here for the Ge/Si core/shell NW system the first experimental measurement of critical shell thickness for strain relaxation in a semiconductor NW heterostructure and the identification of the relaxation mechanisms. Axial and tangential strain relief is initiated by the formation of periodic a/2 〈110〉 perfect dislocations via nucleation and glide on {111} slip-planes. Glide of dislocation segments is directly confirmed by real-time in situ transmission electron microscope observations and by dislocation dynamics simulations. Further shell growth leads to roughening and grain formation which provides additional strain relief. As a consequence of core/shell strain sharing in NWs, a 16 nm radius Ge NW with a 3 nm Si shell is shown to accommodate 3% coherent strain at equilibrium, a factor of 3 increase over the 1 nm equilibrium critical thickness for planar Si/Ge heteroepitaxial growth. © 2012 American Chemical Society.

Internal quantum efficiency and tunable colour temperature in monolithic white InGaN/GaN LED

Internal Quantum Efficiency (IQE) of two-colour monolithic white light emitting diode (LED) was measured by temperature dependant electro-luminescence (TDEL) and analysed with modified rate equation based on ABC model. External, internal and injection efficiencies of blue and green quantum wells were analysed separately. Monolithic white LED contained one green InGaN QW and two blue QWs being separated by GaN barrier. This paper reports also the tunable behaviour of correlated colour temperature (CCT) in pulsed operation mode and effect of self-heating on device performance. © 2014 SPIE.