CDNF and MANF in an experimental model of Parkinson's disease in rats

Parkinson s disease (PD) is a neurodegenerative disorder associated with a progressive loss of dopaminergic neurons of the substantia nigra (SN). Current therapies of PD do not stop the progression of the disease and the efficacy of these treatments wanes over time. Neurotrophic factors are naturally occurring proteins promoting the survival and differentiation of neurons and the maintenance of neuronal contacts. Neurotrophic factors are attractive candidates for neuroprotective or even neurorestorative treatment of PD. Thus, searching for and characterizing trophic factors are highly important approaches to degenerative diseases. CDNF (cerebral dopamine neurotrophic factor) and MANF (mesencephalic astrocyte-derived neurotrophic factor) are secreted proteins that constitute a novel, evolutionarily conserved neurotrophic factor family expressed in vertebrates and invertebrates. The present study investigated the neuroprotective and restorative effects of human CDNF and MANF in rats with unilateral partial lesion of dopamine neurons by 6-hydroxydopamine (6-OHDA) using both behavioral (amphetamine-induced rotation) and immunohistochemical analyses. We also investigated the distribution and transportation profiles of intrastriatally injected CDNF and MANF in rats. Intrastriatal CDNF and MANF protected nigrostriatal dopaminergic neurons when administered six hours before or four weeks after the neurotoxin 6-OHDA. More importantly, the function of the lesioned nigrostriatal dopaminergic system was partially restored even when the neurotrophic factors were administered four weeks after 6-OHDA. A 14-day continuous infusion of CDNF but not of MANF restored the function of the midbrain neural circuits controlling movement when initiated two weeks after unilateral injection of 6-OHDA. Continuous infusion of CDNF also protected dopaminergic TH-positive cell bodies from toxin-induced degeneration in the substantia nigra pars compacta (SNpc) and fibers in the striatum. When injected into the striatum, CDNF and GDNF had similar transportation profiles from the striatum to the SNpc; thus CDNF may act via the same nerve tracts as GDNF. Intrastriatal MANF was transported to cortical areas which may reflect a mechanism of neurorestorative action that is different from that of CDNF and GDNF. CDNF and MANF were also shown to distribute more readily than GDNF. In conclusion, CDNF and MANF are potential therapeutic proteins for the treatment of PD.

Language and the Circuits of Power in a Merging Multinational Corporation

We argue in this paper that corporate language policies have significant power implications that are easily overlooked. By drawing on previous work on power in organizations (Clegg, 1989), we examine the complex power implications of language policy decisions by looking at three levels of analysis: episodic social interaction, identity/subjectivity construction, and reconstruction of structures of domination. In our empirical analysis, we focus on the power implications of the choice of Swedish as the corporate language in the case of the recent banking sector merger between the Finnish Merita and the Swedish Nordbanken. Our findings show how language skills become empowering or disempowering resources in organizational communication, how these skills are associated with professional competence, and how this leads to the creation of new social networks. The case also illustrates how language skills are an essential element in the construction of international confrontation, lead to a construction of superiority and inferiority, and also reproduce post-colonial identities in the merging bank. Finally, we also point out how such policies ultimately lead to the reification of post-colonial and neo-colonial structures of domination in multinational corporations.

Language and the circuits of power in a merging multinational corporation

We argue in this paper that corporate language policies have significant power implications that are easily overlooked. By drawing on previous work on power in organizations (Clegg, 1989), we examine the complex power implications of language policy decisions by looking at three levels of analysis: episodic social interaction, identity/subjectivity construction, and reconstruction of structures of domination. In our empirical analysis, we focus on the power implications of the choice of Swedish as the corporate language in the case of the recent banking sector merger between the Finnish Merita and the Swedish Nordbanken. Our findings show how language skills become empowering or disempowering resources in organizational communication, how these skills are associated with professional competence, and how this leads to the creation of new social networks. The case also illustrates how language skills are an essential element in the construction of international confrontation, lead to a construction of superiority and inferiority, and also reproduce post-colonial identities in the merging bank. Finally, we also point out how such policies ultimately lead to the reification of post-colonial and neo-colonial structures of domination in multinational corporations.

Low Power continuous time common mode sensing for common mode feedback circuits

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 mu m CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27-34% less power than previous high swing CMFB circuits.

Al/SiC carriers for microwave integrated circuits by a new technique of pressureless infiltration

Materials with high thermal conductivity and thermal expansion coefficient matching with that of Si or GaAs are being used for packaging high density microcircuits due to their ability of faster heat dissipation. Al/SiC is gaining wide acceptance as electronic packaging material due to the fact that its thermal expansion coefficient can be tailored to match with that of Si or GaAs by varying the Al:SiC ratio while maintaining the thermal conductivity more or less the same. In the present work, Al/SiC microwave integrated circuit (MIC) carriers have been fabricated by pressureless infiltration of Al-alloy into porous SiC preforms in air. This new technique provides a cheaper alternative to pressure infiltration or pressureless infiltration in nitrogen in producing Al/SiC composites for electronic packaging applications. Al-alloy/65vol% SiC composite exhibited a coefficient of thermal expansion of 7 x 10(-6) K-1 (25 degrees C-100 degrees C) and a thermal conductivity of 147 Wm(-1) K-1 at 30 degrees C. The hysteresis observed in thermal expansion coefficient of the composite in the temperature range 100 degrees C-400 degrees C has been attributed to the presence of thermal residual stresses in the composite. Thermal diffusivity of the composite measured over the temperature range from 30 degrees C to 400 degrees C showed a 55% decrease in thermal diffusivity with temperature. Such a large decrease in thermal diffusivity with temperature could be due to the presence of micropores, microcracks, and decohesion of the Al/SiC interfaces in the microstructure (all formed during cooling from the processing temperature). The carrier showed satisfactory performance after integrating it into a MIC.

Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor-single electron transistor integrated circuits

For the first time, the impact of energy quantisation in single electron transistor (SET) island on the performance of hybrid complementary metal oxide semiconductor (CMOS)-SET transistor circuits has been studied. It has been shown through simple analytical models that energy quantisation primarily increases the Coulomb Blockade area and Coulomb Blockade oscillation periodicity of the SET device and thus influences the performance of hybrid CMOS-SET circuits. A novel computer aided design (CAD) framework has been developed for hybrid CMOS-SET co-simulation, which uses Monte Carlo (MC) simulator for SET devices along with conventional SPICE for metal oxide semiconductor devices. Using this co-simulation framework, the effects of energy quantisation have been studied for some hybrid circuits, namely, SETMOS, multiband voltage filter and multiple valued logic circuits. Although energy quantisation immensely deteriorates the performance of the hybrid circuits, it has been shown that the performance degradation because of energy quantisation can be compensated by properly tuning the bias current of the current-biased SET devices within the hybrid CMOS-SET circuits. Although this study is primarily done by exhaustive MC simulation, effort has also been put to develop first-order compact model for SET that includes energy quantisation effects. Finally, it has been demonstrated that one can predict the SET behaviour under energy quantisation with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique

The increasing variability in device leakage has made the design of keepers for wide OR structures a challenging task. The conventional feedback keepers (CONV) can no longer improve the performance of wide dynamic gates for the future technologies. In this paper, we propose an adaptive keeper technique called rate sensing keeper (RSK) that enables faster switching and tracks the variation across different process corners. It can switch upto 1.9x faster (for 20 legs) than CONV and can scale upto 32 legs as against 20 legs for CONV in a 130-nm 1.2-V process. The delay tracking is within 8% across the different process corners. We demonstrate the circuit operation of RSK using a 32 x 8 register file implemented in an industrial 130-nm 1.2-V CMOS process. The performance of individual dynamic logic gates are also evaluated on chip for various keeper techniques. We show that the RSK technique gives superior performance compared to the other alternatives such as Conditional Keeper (CKP) and current mirror-based keeper (LCR).

In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits

An in-situ power monitoring technique for Dynamic Voltage and Threshold scaling (DVTS) systems is proposed which measures total power consumed by load circuit using sleep transistor acting as power sensor. Design details of power monitor are examined using simulation framework in UMC 90nm CMOS process. Experimental results of test chip fabricated in AMS 0.35µm CMOS process are presented. The test chip has variable activity between 0.05 and 0.5 and has PMOS VTH control through nWell contact. Maximum resolution obtained from power monitor is 0.25mV. Overhead of power monitor in terms of its power consumption is 0.244 mW (2.2% of total power of load circuit). Lastly, power monitor is used to demonstrate closed loop DVTS system. DVTS algorithm shows 46.3% power savings using in-situ power monitor.

Circuits on cylinders

We consider the computational power of constant width polynomial size cylindrical circuits and non deterministic branching programs. We show that every function computed by a Pi(2) o MOD o AC(0) circuit can also be computed by a constant width polynomial size cylindrical nondeterministic branching program (or cylindrical circuit) and that every function computed by a constant width polynomial size cylindrical circuit belongs to ACC(0).

On synthesis of easily testable (k, K) circuits

A (k-, K) circuit is one which can be decomposed into nonintersecting blocks of gates where each block has no more than K external inputs, such that the graph formed by letting each block be a node and inserting edges between blocks if they share a signal line, is a partial k-tree. (k, K) circuits are special in that they have been shown to be testable in time polynomial in the number of gates in the circuit, and are useful if the constants k and K are small. We demonstrate a procedure to synthesise (k, K) circuits from a special class of Boolean expressions.

A low power, process invariant keeper design for high speed dynamic logic circuits

A low power keeper circuit using the concept of rate sensing has been proposed. The proposed technique reduces the amount of short circuit power dissipation in the domino gate by 70% compared to the conventional keeper technique. Also the total power-delay product is 26% lower compared to the previously reported techniques. The process tracking capability of the design enables the domino gate to achieve uniform delay across different process corners. This reduces the amount of short circuit power dissipation that occurs in the cascaded domino gates by 90%. The use of the proposed technique in the read path of a register file reduces the energy requirement by 26% as compared to the other keeper techniques. The proposed technique has been prototyped in 130nm CMOS technology.

Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits

Abstract—A method of testing for parametric faults of analog circuits based on a polynomial representaion of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies apart from DC. Classification of CUT is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. The method needs very little augmentation of circuit to make it testable as only output parameters are used for classification. This procedure is shown to uncover several parametric faults causing smaller than 5 % deviations the nominal values. Fault diagnosis based upon sensitivity of polynomial coefficients at relevant frequencies is also proposed.

V-Transform: “An Enhanced Polynomial Coefficient Based DC Test for Non-linear Analog Circuits

Abstract—DC testing of parametric faults in non-linear analog circuits based on a new transformation, entitled, V-Transform acting on polynomial coefficient expansion of the circuit function is presented. V-Transform serves the dual purpose of monotonizing polynomial coefficients of circuit function expansion and increasing the sensitivity of these coefficients to circuit parameters. The sensitivity of V-Transform Coefficients (VTC) to circuit parameters is up to 3x-5x more than sensitivity of polynomial coefficients. As a case study, we consider a benchmark elliptic filter to validate our method. The technique is shown to uncover hitherto untestable parametric faults whose sizes are smaller than 10 % of the nominal values. I.