On synthesis of easily testable (k, K) circuits
Data(s) |
01/11/2003
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Resumo |
A (k-, K) circuit is one which can be decomposed into nonintersecting blocks of gates where each block has no more than K external inputs, such that the graph formed by letting each block be a node and inserting edges between blocks if they share a signal line, is a partial k-tree. (k, K) circuits are special in that they have been shown to be testable in time polynomial in the number of gates in the circuit, and are useful if the constants k and K are small. We demonstrate a procedure to synthesise (k, K) circuits from a special class of Boolean expressions. |
Formato |
application/pdf |
Identificador |
http://eprints.iisc.ernet.in/40157/1/On_Synthesis_of.pdf Naidu, Srinath R and Chandru, Vijay (2003) On synthesis of easily testable (k, K) circuits. In: IEEE Transactions on Computers, 52 (11). pp. 1490-1494. |
Publicador |
IEEE |
Relação |
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1244946&tag=1 http://eprints.iisc.ernet.in/40157/ |
Palavras-Chave | #Computer Science & Automation (Formerly, School of Automation) |
Tipo |
Journal Article PeerReviewed |