An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

An asymmetric MOSFET-C band-pass filter(BPF)with on chip charge pump auto-tuning is presented.It is implemented in UMC (United Manufacturing Corporation)0.18μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump OUtputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point(HP3) is 16.621 dBm,wim 50 Ω as the source impedance. The input referred noise iS about 47.455μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm~2 and it can be utilized in GPS (global positioning system)and Bluetooth systems.

Modified Holographic Exposure to Fabricate Varied Bragg Grating in an Identical Chip

A new fabricating method is demonstrated to realize two different Bragg gratings in an identical chip using traditional holographic exposure. Polyimide is used to protect one Bragg grating during the first period. The technical process of this method is as simple as that of standard holographic exposure

Multiple Quantum Well SEED Arrays for Flip-Chip Bonding Optoelectronic Smart Pixels

于2010-11-23批量导入

Optoelectronic Smart Pixels Comprising Flip-Chip-Bonded GaAs/AlGaAs MQW Detectors and Modulators on Silicon CMOS Circuit

于2010-11-23批量导入

16-channel VCSEL based multiple chip modules

　

VCSEL based optoelectronic multiple chip modules

We report on optoelectronic multiple chip modules, consisting of vertical cavity surface emitting laser(VCSEL), photodetector and 1.2 mum CMOS electronic circuit, The hybrid integrated components operate at a date rate of 155Mb/s, which could be used in optical interconnects for multiple computers.

Flip-chip bonded hybrid CMOS/SEED optoelectronic smart pixels

Hybrid integration of GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays are demonstrated flip-chip bonded directly onto 1 mu m silicon CMOS circuits. The GaAs/AlGaAs MQW devices are designed for 850 nm operation. Some devices are used as input light detectors and others serve as output light modulators. The measurement results under applied biases show good optoelectronic characteristics of elements in SEED arrays. Nearly the same reflection spectrum is obtained for the different devices at an array and the contrast ratio is more than 1.2:1 after flip-chip bonding and packaging. The transimpedance receiver-transmitter circuit can be operated at a frequency of 300 MHz.

Injection by hydrostatic pressure in conjunction with electrokinetic force on a microfluidic chip

A simple method was developed for injecting a sample on a cross-form microfluidic chip by means of hydrostatic pressure combined with electrokinetic forces. The hydrostatic pressure was generated simply by adjusting the liquid level in different reservoirs without any additional driven equipment such as a pump. Two dispensing strategies using a floating injection and a gated injection, coupled with hydrostatic pressure loading, were tested. The fluorescence observation verified the feasibility of hydrostatic pressure loading in the separation of a mixture of fluorescein sodium salt and fluorescein isothiocyanate. This method was proved to be effective in leading cells to a separation channel for single cell analysis.

Determination of SARS-coronavirus by a microfluidic chip system

We have developed a new experimental system based on a microfluidic chip to determine severe acute respiratory syndrome coronavirus (SARS-Cov). The system includes a laser-induced fluorescence microfluidic chip analyzer, a glass microchip for both polymerase chain reaction (PCR) and capillary electrophoresis, a chip thermal cycler based on dual Peltier thermoelectric elements, a reverse transcription-polymerase chain reaction (RT-PCR) SARS diagnostic kit, and a DNA electrophoretic sizing kit. The system allows efficient cDNA amplification of SARS-CoV followed by electrophoretic sizing and detection on the same chip. To enhance the reliability of RT-PCR on SARS-CoV detection, duplex PCR was developed on the microchip. The assay was carried out on a home-made microfluidic chip system. The positive and the negative control were cDNA fragments of SARS-CoV and parainfluenza virus, respectively. The test results showed that 17 positive samples were obtained among 18 samples of nasopharyngeal swabs from clinically diagnosed SARS patients. However, 12 positive results from the same 18 samples were obtained by the conventional RT-PCR with agarose gel electrophoresis detection. The SARS virus species can be analyzed with high positive rate and rapidity on the microfluidic chip system.

Integrated lectin affinity microfluidic chip for glycoform separation

Lectin affinity chromatography was miniaturized into a microfluidic format, which results in improvement of performance, as compared to the conventional method. A lectin affinity monolith column was prepared in the microchannel of a microfluidic chip. The porous monolith was fabricated by UV-initiated polymerization of ethylene dimethacrylate (EDMA) and glycidyl methacrylate (GMA) in the presence of porogeneities, followed by immobilization of pisum sativum agglutinin (PSA) on the monolith matrix. Using electroosmosis as the driven force, lectin affinity chromatographies of three kinds of glycoprotein, turkey ovalbumin (TO), chicken ovalbumin (CO), and ovomucoid (OM), were carried out on the microfluidic system. All the glycoproteins were successfully separated into several fractions with different affinities toward the immobilized PSA. The integrated system reduces the time required for the lectin affinity chromatography reaction to similar to3%, thus, the overall analysis time from 4 h to 400 s. Only 300 pg of glycoprotein is required for the whole separation process. Moreover, troublesome operations for lectin affinity chromatography are simplified.

An Analog VLSI Chip for Estimating the Focus of Expansion

For applications involving the control of moving vehicles, the recovery of relative motion between a camera and its environment is of high utility. This thesis describes the design and testing of a real-time analog VLSI chip which estimates the focus of expansion (FOE) from measured time-varying images. Our approach assumes a camera moving through a fixed world with translational velocity; the FOE is the projection of the translation vector onto the image plane. This location is the point towards which the camera is moving, and other points appear to be expanding outward from. By way of the camera imaging parameters, the location of the FOE gives the direction of 3-D translation. The algorithm we use for estimating the FOE minimizes the sum of squares of the differences at every pixel between the observed time variation of brightness and the predicted variation given the assumed position of the FOE. This minimization is not straightforward, because the relationship between the brightness derivatives depends on the unknown distance to the surface being imaged. However, image points where brightness is instantaneously constant play a critical role. Ideally, the FOE would be at the intersection of the tangents to the iso-brightness contours at these "stationary" points. In practice, brightness derivatives are hard to estimate accurately given that the image is quite noisy. Reliable results can nevertheless be obtained if the image contains many stationary points and the point is found that minimizes the sum of squares of the perpendicular distances from the tangents at the stationary points. The FOE chip calculates the gradient of this least-squares minimization sum, and the estimation is performed by closing a feedback loop around it. The chip has been implemented using an embedded CCD imager for image acquisition and a row-parallel processing scheme. A 64 x 64 version was fabricated in a 2um CCD/ BiCMOS process through MOSIS with a design goal of 200 mW of on-chip power, a top frame rate of 1000 frames/second, and a basic accuracy of 5%. A complete experimental system which estimates the FOE in real time using real motion and image scenes is demonstrated.

A Parallel Crossbar Routing Chip for a Shared Memory Multiprocessor

This thesis describes the design and implementation of an integrated circuit and associated packaging to be used as the building block for the data routing network of a large scale shared memory multiprocessor system. A general purpose multiprocessor depends on high-bandwidth, low-latency communications between computing elements. This thesis describes the design and construction of RN1, a novel self-routing, enhanced crossbar switch as a CMOS VLSI chip. This chip provides the basic building block for a scalable pipelined routing network with byte-wide data channels. A series of RN1 chips can be cascaded with no additional internal network components to form a multistage fault-tolerant routing switch. The chip is designed to operate at clock frequencies up to 100Mhz using Hewlett-Packard's HP34 $1.2\\mu$ process. This aggressive performance goal demands that special attention be paid to optimization of the logic architecture and circuit design.

Interface of chip-based capillary electrophoresis-inductively coupled plasma-atomic emission spectrometry (CE-ICP-AES)

An interface of chip-based capillary electrophoresis (CE)-inductively coupled plasma-atomic emission spectrometry (ICP-AES) that is based on cross-flow nebulization has been developed. A polydimethylsiloxane (PDMS) CE-chip with conventional cross channel layout was used. A stainless steel tube was placed orthogonal to the exit of the CE separation channel for cross flow nebulization. A supplementary flow of buffer solution at the channel exit was used to improve nebulization efficiency. Two capillaries were inserted into the CE chip near the inlet of the separation channel for sample and buffer solution injection. Syringe pumps were used to manipulate the flow rate and flow direction of the sample, buffer, and supplementary buffer solution. Peak broadening due to the shape (bulb and tube-shaped) and size of the spray chambers was studied. The smaller tube-shaped spray chamber was used because of smaller peak broadening effect due to aerosol transport. The nebulization and transport efficiency of the CE-ICP interface was approximately 10%. Ba2+ and Mg2+ ions were eluted from the CE-chip within 30 s. Resolution of the Ba2+ and Mg2+ peaks was 0.7 using the chip-based CE-ICP-AES system.

Effect of solder volume on joint shape with variable chip-to-board contact pad ratio

The objective of this paper is to investigate the effect of the pad size ratio between the chip and board end of a solder joint on the shape of that solder joint in combination with the solder volume available. The shape of the solder joint is correlated to its reliability and thus of importance. For low density chip bond pad applications Flip Chip (FC) manufacturing costs can be kept down by using larger size board pads suitable for solder application. By using “Surface Evolver” software package the solder joint shapes associated with different size/shape solder preforms and chip/board pad ratios are predicted. In this case a so called Flip-Chip Over Hole (FCOH) assembly format has been used. Assembly trials involved the deposition of lead-free 99.3Sn0.7Cu solder on the board side, followed by reflow, an underfill process and back die encapsulation. During the assembly work pad off-sets occurred that have been taken into account for the Surface Evolver solder joint shape prediction and accurately matched the real assembly. Overall, good correlation was found between the simulated solder joint shape and the actual fabricated solder joint shapes. Solder preforms were found to exhibit better control over the solder volume. Reflow simulation of commercially available solder preform volumes suggests that for a fixed stand-off height and chip-board pad ratio, the solder volume value and the surface tension determines the shape of the joint.

A simulation-based design method to transfer surface mount RF system to flip-chip die implementation

The flip-chip technology is a high chip density solution to meet the demand for very large scale integration design. For wireless sensor node or some similar RF applications, due to the growing requirements for the wearable and implantable implementations, flip-chip appears to be a leading technology to realize the integration and miniaturization. In this paper, flip-chip is considered as part of the whole system to affect the RF performance. A simulation based design is presented to transfer the surface mount PCB board to the flip-chip die package for the RF applications. Models are built by Q3D Extractor to extract the equivalent circuit based on the parasitic parameters of the interconnections, for both bare die and wire-bonding technologies. All the parameters and the PCB layout and stack-up are then modeled in the essential parts' design of the flip-chip RF circuit. By implementing simulation and optimization, a flip-chip package is re-designed by the parameters given by simulation sweep. Experimental results fit the simulation well for the comparison between pre-optimization and post-optimization of the bare die package's return loss performance. This design method could generally be used to transfer any surface mount PCB to flip-chip package for the RF systems or to predict the RF specifications of a RF system using the flip-chip technology.