Electrochemical Immunosensing of Cortisol in an Automated Microfluidic System Towards Point-of-Care Applications

This dissertation describes the development of a label-free, electrochemical immunosensing platform integrated into a low-cost microfluidic system for the sensitive, selective and accurate detection of cortisol, a steroid hormone co-related with many physiological disorders. Abnormal levels of cortisol is indicative of conditions such as Cushing’s syndrome, Addison’s disease, adrenal insufficiencies and more recently post-traumatic stress disorder (PTSD). Electrochemical detection of immuno-complex formation is utilized for the sensitive detection of Cortisol using Anti-Cortisol antibodies immobilized on sensing electrodes. Electrochemical detection techniques such as cyclic voltammetry (CV) and electrochemical impedance spectroscopy (EIS) have been utilized for the characterization and sensing of the label-free detection of Cortisol. The utilization of nanomaterial’s as the immobilizing matrix for Anti-cortisol antibodies that leads to improved sensor response has been explored. A hybrid nano-composite of Polyanaline-Ag/AgO film has been fabricated onto Au substrate using electrophoretic deposition for the preparation of electrochemical immunosening of cortisol. Using a conventional 3-electrode electrochemical cell, a linear sensing range of 1pM to 1µM at a sensitivity of 66µA/M and detection limit of 0.64pg/mL has been demonstrated for detection of cortisol. Alternately, a self-assembled monolayer (SAM) of dithiobis(succinimidylpropionte) (DTSP) has been fabricated for the modification of sensing electrode to immobilize with Anti-Cortisol antibodies. To increase the sensitivity at lower detection limit and to develop a point-of-care sensing platform, the DTSP-SAM has been fabricated on micromachined interdigitated microelectrodes (µIDE). Detection of cortisol is demonstrated at a sensitivity of 20.7µA/M and detection limit of 10pg/mL for a linear sensing range of 10pM to 200nM using the µIDE’s. A simple, low-cost microfluidic system is designed using low-temperature co-fired ceramics (LTCC) technology for the integration of the electrochemical cortisol immunosensor and automation of the immunoassay. For the first time, the non-specific adsorption of analyte on LTCC has been characterized for microfluidic applications. The design, fabrication technique and fluidic characterization of the immunoassay are presented. The DTSP-SAM based electrochemical immunosensor on µIDE is integrated into the LTCC microfluidic system and cortisol detection is achieved in the microfluidic system in a fully automated assay. The fully automated microfluidic immunosensor hold great promise for accurate, sensitive detection of cortisol in point-of-care applications.

On-Chip Clock Network Skew Measurement using Sub-Sampling

We present a technique for an all-digital on-chip delay measurement system to measure the skews in a clock distribution network. It uses the principle of sub-sampling. Measurements from a prototype fabricated in a 65 nm industrial process, indicate the ability to measure delays with a resolution of 0.5ps and a DNL of 1.2 ps.

SU-8-Based Microchips for Capillary Electrophoresis and Electrospray Ionization Mass Spectrometry

Miniaturization of analytical instrumentation is attracting growing interest in response to the explosive demand for rapid, yet sensitive analytical methods and low-cost, highly automated instruments for pharmaceutical and bioanalyses and environmental monitoring. Microfabrication technology in particular, has enabled fabrication of low-cost microdevices with a high degree of integrated functions, such as sample preparation, chemical reaction, separation, and detection, on a single microchip. These miniaturized total chemical analysis systems (microTAS or lab-on-a-chip) can also be arrayed for parallel analyses in order to accelerate the sample throughput. Other motivations include reduced sample consumption and waste production as well as increased speed of analysis. One of the most promising hyphenated techniques in analytical chemistry is the combination of a microfluidic separation chip and mass spectrometer (MS). In this work, the emerging polymer microfabrication techniques, ultraviolet lithography in particular, were exploited to develop a capillary electrophoresis (CE) separation chip which incorporates a monolithically integrated electrospray ionization (ESI) emitter for efficient coupling with MS. An epoxy photoresist SU-8 was adopted as structural material and characterized with respect to its physicochemical properties relevant to chip-based CE and ESI/MS, namely surface charge, surface interactions, heat transfer, and solvent compatibility. As a result, SU-8 was found to be a favorable material to substitute for the more commonly used glass and silicon in microfluidic applications. In addition, an infrared (IR) thermography was introduced as direct, non-intrusive method to examine the heat transfer and thermal gradients during microchip-CE. The IR data was validated through numerical modeling. The analytical performance of SU-8-based microchips was established for qualitative and quantitative CE-ESI/MS analysis of small drug compounds, peptides, and proteins. The CE separation efficiency was found to be similar to that of commercial glass microchips and conventional CE systems. Typical analysis times were only 30-90 s per sample indicating feasibility for high-throughput analysis. Moreover, a mass detection limit at the low-attomole level, as low as 10E+5 molecules, was achieved utilizing MS detection. The SU-8 microchips developed in this work could also be mass produced at low cost and with nearly identical performance from chip to chip. Until this work, the attempts to combine CE separation with ESI in a chip-based system, amenable to batch fabrication and capable of high, reproducible analytical performance, have not been successful. Thus, the CE-ESI chip developed in this work is a substantial step toward lab-on-a-chip technology.

System-level analysis of network interfaces for hierarchical MPSoCs

Network Interfaces (NIs) are used in Multiprocessor System-on-Chips (MPSoCs) to connect CPUs to a packet switched Network-on-Chip. In this work we introduce a new NI architecture for our hierarchical CoreVA-MPSoC. The CoreVA-MPSoC targets streaming applications in embedded systems. The main contribution of this paper is a system-level analysis of different NI configurations, considering both software and hardware costs for NoC communication. Different configurations of the NI are compared using a benchmark suite of 10 streaming applications. The best performing NI configuration shows an average speedup of 20 for a CoreVA-MPSoC with 32 CPUs compared to a single CPU. Furthermore, we present physical implementation results using a 28 nm FD-SOI standard cell technology. A hierarchical MPSoC with 8 CPU clusters and 4 CPUs in each cluster running at 800MHz requires an area of 4.56mm2.

A method of tracking the peak power points for a variable speed wind energy conversion system

In this paper, a method of tracking the peak power in a wind energy conversion system (WECS) is proposed, which is independent of the turbine parameters and air density. The algorithm searches for the peak power by varying the speed in the desired direction. The generator is operated in the speed control mode with the speed reference being dynamically modified in accordance with the magnitude and direction of change of active power. The peak power points in the P-omega curve correspond to dP/domega = 0. This fact is made use of in the optimum point search algorithm. The generator considered is a wound rotor induction machine whose stator is connected directly to the grid and the rotor is fed through back-to-back pulse-width-modulation (PWM) converters. Stator flux-oriented vector control is applied to control the active and reactive current loops independently. The turbine characteristics are generated by a dc motor fed from a commercial dc drive. All of the control loops are executed by a single-chip digital signal processor (DSP) controller TMS320F240. Experimental results show that the performance of the control algorithm compares well with the conventional torque control method.

Fault-Tolerant Average Execution Time Optimization for General Purpose Multi-Processor System-on Chips

Fault-tolerance is due to the semiconductor technology development important, not only for safety-critical systems but also for general-purpose (non-safety critical) systems. However, instead of guaranteeing that deadlines always are met, it is for general-purpose systems important to minimize the average execution time (AET) while ensuring fault-tolerance. For a given job and a soft (transient) error probability, we define mathematical formulas for AET that includes bus communication overhead for both voting (active replication) and rollback-recovery with checkpointing (RRC). And, for a given multi-processor system-on-chip (MPSoC), we define integer linear programming (ILP) models that minimize AET including bus communication overhead when: (1) selecting the number of checkpoints when using RRC, (2) finding the number of processors and job-to-processor assignment when using voting, and (3) defining fault-tolerance scheme (voting or RRC) per job and defining its usage for each job. Experiments demonstrate significant savings in AET.

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

An Accurate Fractional Period Delay Generation System

An all-digital technique is proposed for generating an accurate delay irrespective of the inaccuracies of a controllable delay line. A subsampling technique-based delay measurement unit (DMU) capable of measuring delays accurately for the full period range is used as the feedback element to build accurate fractional period delays based on input digital control bits. The proposed delay generation system periodically measures and corrects the error and maintains it at the minimum value without requiring any special calibration phase. Up to 40x improvement in accuracy is demonstrated for a commercial programmable delay generator chip. The time-precision trade-off feature of the DMU is utilized to reduce the locking time. Loop dynamics are adjusted to stabilize the delay after the minimum error is achieved, thus avoiding additional jitter. Measurement results from a high-end oscilloscope also validate the effectiveness of the proposed system in improving accuracy.

Applying Genetic Algorithms to Optimize Power in Tiled SNUCA Chip Multicore Architectures

We propose a novel technique for reducing the power consumed by the on-chip cache in SNUCA chip multicore platform. This is achieved by what we call a "remap table", which maps accesses to the cache banks that are as close as possible to the cores, on which the processes are scheduled. With this technique, instead of using all the available cache, we use a portion of the cache and allocate lesser cache to the application. We formulate the problem as an energy-delay (ED) minimization problem and solve it offline using a scalable genetic algorithm approach. Our experiments show up to 40% of savings in the memory sub-system power consumption and 47% savings in energy-delay product (ED).

Applying Genetic Algorithms to Optimize Power in Tiled SNUCA Chip Multicore Architectures

We propose a novel technique for reducing the power consumed by the on-chip cache in SNUCA chip multicore platform. This is achieved by what we call a "remap table", which maps accesses to the cache banks that are as close as possible to the cores, on which the processes are scheduled. With this technique, instead of using all the available cache, we use a portion of the cache and allocate lesser cache to the application. We formulate the problem as an energy-delay (ED) minimization problem and solve it offline using a scalable genetic algorithm approach. Our experiments show up to 40% of savings in the memory sub-system power consumption and 47% savings in energy-delay product (ED).

Analysis of integrated optofluidic lab-on-a-chip sensor based on refractive index and absorbance sensing

The analysis of a fully integrated optofluidic lab-on-a-chip sensor is presented in this paper. This device is comprised of collinear input and output waveguides that are separated by a microfluidic channel. When light is passed through the analyte contained in the fluidic gap, optical power loss occurs owing to absorption of light. Apart from absorption, a mode-mismatch between the input and output waveguides occurs when the light propagates through the fluidic gap. The degree of mode-mismatch and quantum of optical power loss due to absorption of light by the fluid form the basis of our analysis. This sensor can detect changes in refractive index and changes in concentration of species contained in the analyte. The sensitivity to detect minute changes depends on many parameters. The parameters that influence the sensitivity of the sensor are mode spot size, refractive index of the fluid, molar concentration of the species contained in the analyte, width of the fluidic gap, and waveguide geometry. By correlating various parameters, an optimal fluidic gap distance corresponding to a particular mode spot size that achieves the best sensitivity is determined both for refractive index and absorbance-based sensing.

MRT Letter: Light Sheet Based Imaging Flow Cytometry on a Microfluidic Platform

We propose a light sheet based imaging flow cytometry technique for simultaneous counting and imaging of cells on a microfluidic platform. Light sheet covers the entire microfluidic channel and thus omits the necessity of flow focusing and point scanning based technology. Another advantage lies in the orthogonal detection geometry that totally cuts-off the incident light, thereby substantially reducing the background in the detection. Compared to the existing state-of-art techniques the proposed technique shows marked improvement. Using fluorescently-coated Saccharomyces cerevisiae cells we have recorded cell counting with throughput as high as 2,090 cells/min in the low flow rate regime and were able to image the individual cells on-the-go. Overall, the proposed system is cost-effective and simple in channel geometry with the advantage of efficient counting in operational regime of low laminar flow. This technique may advance the emerging field of microfluidic based cytometry for applications in nanomedicine and point of care diagnostics. Microsc. Res. Tech. 76:1101-1107, 2013. (c) 2013 Wiley Periodicals, Inc.

System-level SoC near-field (NF) emissions: Simulation to measurement correlation

As System-on-Chip (SoC) designs migrate to 28nm process node and beyond, the electromagnetic (EM) co-interactions of the Chip-Package-Printed Circuit Board (PCB) becomes critical and require accurate and efficient characterization and verification. In this paper a fast, scalable, and parallelized boundary element based integral EM solutions to Maxwell equations is presented. The accuracy of the full-wave formulation, for complete EM characterization, has been validated on both canonical structures and real-world 3-D system (viz. Chip + Package + PCB). Good correlation between numerical simulation and measurement has been achieved. A few examples of the applicability of the formulation to high speed digital and analog serial interfaces on a 45nm SoC are also presented.

High resolution light-sheet based high-throughput imaging cytometry system enables visualization of intra-cellular organelles

Visualization of intracellular organelles is achieved using a newly developed high throughput imaging cytometry system. This system interrogates the microfluidic channel using a sheet of light rather than the existing point-based scanning techniques. The advantages of the developed system are many, including, single-shot scanning of specimens flowing through the microfluidic channel at flow rate ranging from micro-to nano- lit./min. Moreover, this opens-up in-vivo imaging of sub-cellular structures and simultaneous cell counting in an imaging cytometry system. We recorded a maximum count of 2400 cells/min at a flow-rate of 700 nl/min, and simultaneous visualization of fluorescently-labeled mitochondrial network in HeLa cells during flow. The developed imaging cytometry system may find immediate application in biotechnology, fluorescence microscopy and nano-medicine. (C) 2014 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution 3.0 Unported License.

Design and Validation of On-chip Planar Mixer Based on Advection and Viscoelastic Effects

Mixing at low Reynolds number is usually due to diffusion and requires longer channel lengths for complete mixing. In order to reduce the mixing lengths, advective flow can be induced by varying the channel geometry. Additionally, in non-newtonian fluids, appropriate modifications to channel geometry can be used to aid the mixing process by capitalizing on their viscoelastic nature. Here we have exploited the advection and viscoelastic effects to implement a planar passive micro-mixer. Microfluidic devices incorporating different blend of mixing geometries were conceived. The optimum design was chosen based on the results of the numerical simulations performed in COMSOL. The chosen design had sudden expansion and contraction along with teeth patterns along the channel walls to improve mixing. Mixing of two different dyes was performed to validate the mixing efficiency. Particle dispersion experiments were also carried out. The results indicated effective mixing. In addition, the same design was also found to be compatible with electrical power free pumping mechanism like suction. The proposed design was then used to carry out on-chip chemical cell lysis with human whole blood samples to establish its use with non-newtonian fluids. Complete lysis of the erythrocytes was observed leaving behind the white blood cells at the outlet.