Structural and optical changes in GaAs/InAs/GaAs structure induced by thermal annealing

Self-organized InAs quantum; dots sheets are grown on GaAs(100) substrate and tapped by 80nm GaAs layer with molecular beam epitaxy. Samples were annealed and characterized with Raman spectra, transmission electron microscopy (TEM) and photolumincscence (PL). The Raman spectra indicates arsenic clusters in the GaAs capping layer. The TEM analysis revealed the relaxation of strain in some InAs islands with the introduction of the network of 90 dislocations. In addition, the structural changes also lead to the changes of the PL spectra from me InAs islands. Their correlation was discussed, Our results suggest:est that annealing may be used to intentionally modify me properties of self-organized InAs islands on GaAs.

Iron related emission spectra in InP

This paper presents a detailed PL study of Fe2+ related four zero-phonon(ZP) lines and their related phonon sidebands. Four zero-phonon transitions at approximate to 2800 cm(-1) along with the accompanying phonon sidebands extending down to 2400 cm(-1). There are ta two prominent regions in the phonon sidebands. One is ascribed to coupling to acoustic-type phonons (2700 cm(-1) region), the other is due to coupling to optic-type phonons (2500 cm(-1) region). Beside broad coupling with lattice modes, there are several groups of lines. They are ascribed to resonant modes, impurities induced gap modes and local modes.

Room-temperature continuous-wave lasing from InAs GaAs quantum dot laser grown by molecular beam epitaxy

Quantum dot lasers are predicted to have proved lasing characteristics compared to quantum well and quantum wire lasers. We report on quantum dot lasers with active media of vertically stacked InAs quantum dots layers grown by molecular beam epitaxy. The laser diodes were fabricated and the threshold current density of 220 A/cm(2) was achieved at room temperature with lasing wavelength of 951 nm. The characteristic temperature To was measured to be 333K and 157K for the temperature range of 40-180K and 180-300K, respectively.

Semi-insulating GaAs grown in outer space

A semi-insulating GaAs single crystal ingot was grown in a recoverable satellite, within a specially designed pyrolytic boron nitride crucible, in a power-traveling furnace under microgravity. The characteristics of a compound semiconductor single crystal depends fundamentally on its stoichiometry, i.e. the ration of two types of atoms in the crystal. a practical technique for nondestructive and quantitative measuring stoichiometry in GaAs single crystal was used to analyze the space-grown GaAs single crystal. The distribution of stoichiometry in a GaAs wafer was measured for the first time. The electrical, optical and structural properties of the space-grown GaAs crystal were studied systematically, Device fabricating experiments prove that the quality of field effect transistors fabricated from direct ion-implantation in semi-insulating GaAs wafers has a close correlation with the crystal's stoichiometry. (C) 2000 Elsevier Science S.A. All rights reserved.

硅条探测器前端ASIC芯片测试系统电路设计

介绍一种前端读出专用集成电路(ASIC,Application-Specific Integrated Circuit)芯片性能测试系统的电路设计与实现。该ASIC芯片可用于构成硅微条探测器、硅条、Si(Li)和CsI探测器的前端读出电子学系统。本文详细描述了测试系统的构成,主要电路设计,系统应用以及部分测试结果,并简要介绍了被测ASIC芯片的电路结构。

A low noise charge sensitive preamplifier with switch control feedback resistance

In this paper, the design and analysis of a new low noise charge sensitive preamplifier for silicon strip, Si(Li), CdZnTe and CsI detectors etc. with switch control feedback resistance were described, the entire system to be built using the CMOS transistors. The circuit configuration of the CSP proposed in this paper can be adopted to develop CMOS-based Application Specific Integrated Circuit further for Front End Electronics of read-out system of nuclear physics, particle physics and astrophysics research, etc. This work is an implemented design that we succeed after a simulation to obtain a rise time less than 3ns, the output resistance less than 94 Omega and the linearity almost good.

A Coupled Multi-ALU Processing Node for a Highly Parallel Computer

This report describes Processor Coupling, a mechanism for controlling multiple ALUs on a single integrated circuit to exploit both instruction-level and inter-thread parallelism. A compiler statically schedules individual threads to discover available intra-thread instruction-level parallelism. The runtime scheduling mechanism interleaves threads, exploiting inter-thread parallelism to maintain high ALU utilization. ALUs are assigned to threads on a cycle byscycle basis, and several threads can be active concurrently. Simulation results show that Processor Coupling performs well both on single threaded and multi-threaded applications. The experiments address the effects of memory latencies, function unit latencies, and communication bandwidth between function units.

DC/DC converter 3D assembly for autonomous sensor nodes

This paper reports on the design and the manufacturing of an integrated DCDC converter, which respects the specificity of sensor node network: compactness, high efficiency in acquisition and transmission modes, and compatibility with miniature Lithium batteries. A novel integrated circuit (ASIC) has been designed and manufactured to provide regulated Voltage to the sensor node from miniaturized, thin film Lithium batteries. Then, a 3D integration technique has been used to integrate this ASIC in a 3 layers stack with high efficiency passives components, mixing the wafer level technologies from two different research institutions. Electrical results have demonstrated the feasibility of this integrated system and experiments have shown significant improvements in the case of oscillations in regulated voltage. However, stability of this output voltage toward the input voltage has still to be improved.

Statistical method of modeling and optimization for wireless sensor nodes with different interconnect technologies and substrates

A comparison study was carried out between a wireless sensor node with a bare die flip-chip mounted and its reference board with a BGA packaged transceiver chip. The main focus is the return loss (S parameter S11) at the antenna connector, which was highly depended on the impedance mismatch. Modeling including the different interconnect technologies, substrate properties and passive components, was performed to simulate the system in Ansoft Designer software. Statistical methods, such as the use of standard derivation and regression, were applied to the RF performance analysis, to see the impacts of the different parameters on the return loss. Extreme value search, following on the previous analysis, can provide the parameters' values for the minimum return loss. Measurements fit the analysis and simulation well and showed a great improvement of the return loss from -5dB to -25dB for the target wireless sensor node.

Insertion of metal oxides into block copolymer nanopatterns as robust etch masks for nanolithography

Directed self-assembly (DSA) of block copolymers (BCPs) is a prime candidate to further extend dimensional scaling of silicon integrated circuit features for the nanoelectronic industry. Top-down optical techniques employed for photoresist patterning are predicted to reach an endpoint due to diffraction limits. Additionally, the prohibitive costs for “fabs” and high volume manufacturing tools are issues that have led the search for alternative complementary patterning processes. This thesis reports the fabrication of semiconductor features from nanoscale on-chip etch masks using “high χ” BCP materials. Fabrication of silicon and germanium nanofins via metal-oxide enhanced BCP on-chip etch masks that might be of importance for future Fin-field effect transistor (FinFETs) application are detailed.

Analysis and Synthesis of pHEMT Class-E Amplifiers with Shunt Inductor including ON-State Active-Device Resistance Effects

In this theoretical paper, the analysis of the effect that ON-state active-device resistance has on the performance of a Class-E tuned power amplifier using a shunt inductor topology is presented. The work is focused on the relatively unexplored area of design facilitation of Class-E tuned amplifiers where intrinsically low-output-capacitance monolithic microwave integrated circuit switching devices such as pseudomorphic high electron mobility transistors are used. In the paper, the switching voltage and current waveforms in the presence of ON-resistance are analyzed in order to provide insight into circuit properties such as RF output power, drain efficiency, and power-output capability. For a given amplifier specification, a design procedure is illustrated whereby it is possible to compute optimal circuit component values which account for prescribed switch resistance loss. Furthermore, insight into how ON-resistance affects transistor selection in terms of peak switch voltage and current requirements is described. Finally, a design example is given in order to validate the theoretical analysis against numerical simulation.

Thin film sputtered silicon for silicon wafer bonding applications

The transfer of functional integrated circuit layers to other substrates is being investigated for smart-sensors, MEMS, 3-D ICs and mixed semiconductor circuits. There is a need for a planarisation and bondable layer which can be deposited at low temperature and which is IC compatible. This paper describes for the first time the successful use of sputtered silicon in this role for applications as outlined above where high temperature post bond anneals are not required. It also highlights the problems of using sputtered silicon as a bonding layer in applications where post bond temperatures greater than 400C are required.

Exploring figures of merit associated with the suboptimum operation of class-E power amplifiers

Closed-form design equations for the operation of a class-E amplifier for zero switch voltage slope and arbitrary duty cycle are derived. This approach allows an additional degree of freedom in the design of class-E amplifiers which are normally designed for 50 duty ratio. The analysis developed permits the selection of non-unique solutions where amplifier efficiency is theoretically 100 but power output capability is less than that the 50 duty ratio case would permit. To facilitate comparison between 50 (optimal) and non-50 (suboptimal) duty ratio cases, each important amplifier parameter is normalised to its corresponding optimum operation value. It is shown that by choosing a non-50 suboptimal solution, the operating frequency of a class-E amplifier can be extended. In addition, it is shown that by operating the amplifier in the suboptimal regime, other amplifier parameters, for example, transistor output capacitance or peak switch voltage, can be included along with the standard specification criteria of output power, DC supply voltage and operating frequency as additional input design specifications. Suboptimum class-E operation may have potential advantages for monolithic microwave integrated circuit realisation as lower inductance values (lower series resistance, higher self-resonance frequency, less area) may be required when compared with the results obtained for optimal class-E amplifier synthesis. The theoretical analysis conducted here was verified by harmonic balance simulation, with excellent agreement between both methods. © The Institution of Engineering and Technology 2007.

Even order harmonic Series-L/Parallel-Tuned Class-E frequency multiplier

In this brief, we propose a new Class-E frequency multiplier based on the recently introduced Series-L/Parallel-Tuned Class-E amplifier. The proposed circuit produces even-order output harmonics. Unlike previously reported solutions the proposed circuit can operate under 50% duty ratio which minimizes the conduction losses. The circuit also offers the possibility for increased maximum operating frequency, reduced peak switch voltage, higher load resistance and inherent bond wire absorption; all potentially useful in monolithic microwave integrated circuit implementations. In addition, the circuit topology suggested large transistors with high output capacitances can be deployed. Theoretical design equations are given and the predictions made using these are shown to agree with harmonic balance circuit simulation results.

V-band 57-65 GHz receiver

A simple V-band radio IQ receiver architecture based around a six-port monolithic microwave integrated circuit (MMIC) is presented. The receiver assembly is designed to cover the 57-65 GHz broadband wireless communication system frequency allocation. The receiver that has an integral 10 dB microstrip antenna consumes 120 mW of dc power and occupies an area of 23 mm x 16 mm. The receiver can be used in heterodyne or in homodyne mode and has the capacity to demodulate quadrature amplitude modulation (QAM), binary phase shift keying (BPSK)/quadrature phase shift keying (QPSK)/offset quadrature phase shift keying (OQPSK). At 60 GHz the receiver can operate over 10 m range for transmitter effective isotropic radiated power (EIRP) of 20 dBm.