Efficient Voltage/Current Spike Reduction by Active Gate Signaling

This paper presents an Active Gate Signaling scheme to reduce voltage/current spikes across insulated gate power switches in hard switching power electronic circuits. Voltage and/or current spikes may cause EMI noise. In addition, they increase voltage/current stress on the switch. Traditionally, a higher gate resistance is chosen to reduce voltage/current spikes. Since the switching loss will increase remarkably, an active gate voltage control scheme is developed to improve efficiency of hard switching circuits while the undesirable voltage and/or current spikes are minimized.

A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor

In this work, for the first time, we present a physically based analytical threshold voltage model for omega gate silicon nanowire transistor. This model is developed for long channel cylindrical body structure. The potential distribution at each and every point of the of the wire is derived with a closed form solution of two dimensional Poisson's equation, which is then used to model the threshold voltage. Proposed model can be treated as a generalized model, which is valid for both surround gate and semi-surround gate cylindrical transistors. The accuracy of proposed model is verified for different device geometry against the results obtained from three dimensional numerical device simulators and close agreement is observed.

Growth of SiGe heterojunction bipolar transistor using Si2H6 gas and Ge solid sources molecular beam epitaxy

N-p-n Si/SiGe/Si heterostructure has been grown by a disilane (Si2H6) gas and Ge solid sources molecular beam epitaxy system using phosphine (PH3) and diborane (B2H6) as n- and p-type in situ doping sources, respectively. X-ray diffraction (XRD) and secondary ion mass spectroscopy (SIMS) measurements show that the grown heterostructure has a good quality, the boron doping is confined to the SiGe base layer, and the Ge has a trapezoidal profile. Postgrowth P implantation was performed to prepare a good ohmic contact to the emitter. Heterojunction bipolar transistor (HBT) has been fabricated using the grown heterostructure and a common-emitter current gain of 75 and a cut-off frequency of 20 GHz at 300 K have been obtained. (C) 2001 Elsevier Science B.V. All rights reserved.

The growth of Si/SiGe/Si structures for heterojunction bipolar transistor by gas source molecular beam epitaxy

Three n-p-n Si/SiGe/Si heterostructures with different layer thickness and doping concentration have been grown by a home-made gas source molecular-beam epitaxy (GSMBE) system using phosphine (PH3) and diborane (B2H6) as n-and p-type in situ doping sources, respectively. Heterojunction bipolar transistors (HBTs) have been fabricated using these structures and a current gain of 40 at 300 K and 62 at 77 K have been obtained. The influence of thickness and doping concentration of the deposited layers on the current gain of the HBTs is discussed. (C) 2000 Elsevier Science B.V. All rights reserved.

Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach.

A novel single-phase ZCS-PWM high power factor boost rectifier

This paper presents a novel single-phase high power factor PWM boost rectifier, featuring soft commutation of the active switches at zero-current (ZCS). It incorporates the most desirable properties of the conventional PWM and the soft-switching resonant techniques. The input current shaping is achieved with average current mode control, and continuous inductor current mode. This new PWM converter provides ZCS turn-on and turn-off of the active switches, and it is suitable for high power applications employing IGBTs. Principle of operation, theoretical analysis, a design example, and experimental results from a laboratory prototype rated at 1600 W with 400 Vdc output voltage are presented. The measured efficiency and power factor were 96.2% and 0.99 respectively, with an input current THD equal to 3.94%, for an input voltage THD equal to 3.8%, at rated load.

Material characterization and process development for indium-arsenide / indium-gallium-antimonide channel, high electron mobility transistors for low power, high speed applications

Efforts to push the performance of transistors for millimeter-wave and microwave applications have borne fruit through device size scaling and the use of novel material systems. III-V semiconductors and their alloys hold a distinct advantage over silicon because they have much higher electron mobility which is a prerequisite for high frequency operation. InGaAs/InP pseudomorphic heterojunction bipolar transistors (HBTs) have demonstrated fT of 765 GHz at room temperature and InP based high electron mobility transistors (HEMTs) have demonstrated fMax of 1.2 THz. The 6.1 A lattice family of InAs, GaSb, AlSb covers a wide variety of band gaps and is an attractive future material system for high speed device development. Extremely high electron mobilities ~ 30,000 cm^2 V^-1s^-1 have been achieved in modulation doped InAs-AlSb structures. The work described in this thesis involves material characterization and process development for HEMT fabrication on this material system.

Characterization of strain in Si1-xGex films using multiple angle of incidence ellipsometry

In this letter we characterize strain in Si1-xGex based heterojunction bipolar transistors and modulation doped field effect transistors grown by rapid thermal chemical vapor deposition exploiting the phenomenon of strain-induced birefringence. The technique used is multiple angle of incidence ellipsometry at a wavelength of 670 nm to measure the ordinary and extraordinary refractive indices of the Si1-xGex films. We report measurements on thin fully strained films (with thicknesses less than the critical thickness) with Ge concentration varying from 9% to 40% with an accuracy of the order of 1 part in 10(4) and propose an empirical relation between the difference in the ordinary and extraordinary refractive indices (deltan) and the Ge concentration (x) given by deltan(x)=0.18x-0.12x(2). (C) 2000 American Institute of Physics. [S0003-6951(00)03948-6].

Si, Si-Ge and the new heterostructure world

Semiconductor heterostructures based on AlAs/GaAs and other III-V compounds have been the focus of active research for some time now. Ih the last decade, a new heterostructure material, the strained Si/SiGe system, has emerged. This heterojunction technology can potentially be integrated into the current VLSI environment with large-scale impact in the growing microelectronics market. Si/SiGe heterojunction bipolar transistors with cut-off frequencies exceeding 100 GHz and other electronic and optical devices with superior properties compared to all-Si technology have been demonstrated in laboratories worldwide.

Modeling of the Effects of Process Variations on Circuit Delay at 65nm

A novel methodology for modeling the effects of process variations on circuit delay performance is proposed by relating the variations in process parameters to variations in delay metric of a complex digital circuit. The delay of a 2-input NAND gate with 65nm gate length transistors is extensively characterized by mixed-mode simulations which is then used as a library element. The variation in saturation current Ionat the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. A 4-bit x 4-bit Wallace tree multiplier circuit is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, to obtain delay distributions, by an extensive Monte Carlo analysis. An analytical model based on CV/I metric is proposed, to extend this methodology for a generic technology library with a variety of library elements.

Effect of heavy boron doping on the electrical characteristics of SiGeHBTs

A modified version of the Jain-Roulston (J-R) model is developed that takes into account the compensation effect of B to Ge in strained SiGe layers for the first time. Based on this new model, the distribution of the bandgap narrowing (BGN) between the conduction and valence bands is calculated. The influence of this distribution on the transport characteristics of abrupt SiGe heterojunction bipolar transistors (HBTs) has been further considered by using the tunnelling and thermionic emission mechanisms instead of the drift and diffusion mechanisms at the interfaces where discontinuities in energy levels appear. The results show that our modified J-R model better fits the experimental values, and the energy band structure has a strong influence on electrical characteristics.

Effect of heavily doped boron on bandgap narrowing of strained SiGe layers

Taking into account the compensation effect of B to Ge in strained SiGe layers for the first time, the effect of heavily doped boron on the bandgap narrowing of strained SiGe layers is calculated, and the classical Jain-Roulston (J-R) model is modified. The results show that our modified J-R model well fits the experimental values. Based on the modified J-R model, the real bandgap narrowing distribution between the conduction and valence bands is further calculated, which has great influence on modelling the electrical characteristics of SiGe heterojunction bipolar transistors.

Study on Mg memory effect in npn type AlGaN/GaN HBT structures grown by MOCVD

AlGaN/GaN npn heterojunction bipolar transistor structures were grown by low-pressure MOCVD. Secondary ion mass spectroscopy (SIMS) measurements were carried out to study the Mg memory effect and redistribution in the emitter-base junction. The results indicated that there is a Mg-rich film formed in the ongrowing layer after the Cp2Mg source is switched off. The Mg-rich film can be confined in the base section by switching off the Cp2Mg source for appropriate time before the end of base growth. Low temperature growth of the undoped GaN spacer suppresses the Mg redistribution from Mg rich film. The delay rate of the Mg profile in sample C with spacer growing in low temperature is about 56 nm/decade, which becomes sharper than 80 nm/decade of the samples A and B without low temperature spacer. (C) 2005 Elsevier Ltd. All rights reserved.

High Temperature Characteristics of 3C-SiC/Si Heterojunction Diodes Grown by LPCVD

The high temperature (300～480K) characteristics of the n-3C-SiC/p-Si heterojunction diodes (HJD) fabricated by low-pressure chemical vapor deposition on Si (100) substrates are investigated.The obtained diode with best rectifying properties has 1.8×104 of ratio at room temperature,and slightly rectifying characteristics with 3.1 of rectification ratio is measured at 480K of an ambient temperature .220V of reverse breakdown voltage is acquired at 300K.Capacitance-voltage characteristics show that the abrupt junction model is applicable to the SiC/Si HJD structure and the built-in voltage is 0.75V.An ingenious equation is employed to perfectly simulate and explain the forward current density-voltage data measured at various temperatures.The 3C-SiC/Si HJD represents a promising approach for the fabrication of high quality heterojunction devices such as SiC-emitter heterojunction bipolar transistors.

Heteroepitaxial Growth and Heterojunction Characteristics of Voids-Free n-3C-SiC on p-Si(100)

Highly oriented voids-free 3C-SiC heteroepitaxial layers are grown on φ50mm Si (100) substrates by low pressure chemical vapor deposition (LPCVD). The initial stage of carbonization and the surface morphology of carbonization layers of Si(100) are studied using reflection high energy electron diffraction (RHEED) and scanning electron microscopy (SEM). It is shown that the optimized carbonization temperature for the growth of voids-free 3S-SiC on Si (100) substrates is 1100 ℃. The electrical properties of SiC layers are characterized using Van der Pauw method. The I-V, C-V, and the temperature dependence of I-V characteristics in n-3C-SiC-p-Si heterojunctions with AuGeNi and Al electrical pads are investigated. It is shown that the maximum reverse breakdown voltage of the n-3C-SiC-p-Si heterojunction diodes reaches to 220V at room temperature. These results indicate that the SiC/Si heterojunction diode can be used to fabricate the wide bandgap emitter SiC/Si heterojunction bipolar transistors (HBT's).