车道收费系统中USB接口通信卡的设计

带USB接口的设备使用方便,发展迅速,文章结合高速公路车道收费系统中的实际问题,详细介绍了设计一个USB接口通信卡的过程,包括电路设计、器件选择、固件设计、驱动程序及其应用程序设计。

USB接口技术在数据采集与控制系统中的应用

基于USB接口技术的设备使用方便，发展迅速，文章结合高速公路车道收费系统中所涉及到的数据传输实际问题。详细介绍了设计一个USB接口设备的过程，包括硬件设计、固件设计、驱动程序及其应用程序设计。

CAN总线及USB技术在路桥收费系统中的应用研究

本文以中国科学院沈阳自动化研究所自动化装备研究室的项目——路桥收费系统为背景。首先阐述了路桥收费系统的组成结构，重点讨论了传统的收费控制子系统的构成和功能。然后在深入分析原有系统不足的基础上，本文提出了采用CAN总线技术和USB接口技术来构建一种全新的收费控制子系统的方法。并对这种方法进行了深入的研究，设计并实现了组成系统所需的核心器件，构成了原型系统，对系统的可行性进行了验证。 CAN总线是目前在中小型测控系统中应用非常广泛的总线之一，它非常适用于收费控制子系统中。USB接口技术是近几年来兴起的新型接口技术，它为外围设备与计算机的连接提供了一种方便、快捷的方法。在我们的系统中以基于USB的新型CAN适配卡代替了以往普通的CAN适配卡，为控制计算机联入CAN网开拓了新思路。 本文详细地阐述了系统中核心器件RS232/CAN、CAN/USB协议转换卡的设计与实现及原型系统的构建和测试方法。主要内容分为系统硬件的设计与实现、系统软件的设计与实现和测试系统的设计与调试三部分。具体包括了核心器件的设计原理、电子元器件的选择、电路原理图的设计、PCB板的制作、硬件的焊接与调试及协议转换卡的固件设计、驱动程序设计、上位机测试程序设计。最后利用所设计的软硬件构建了原型系统并进行了测试。

基于DSP和FPGA的火腿肠质量检测系统设计

本文研究的主要内容为基于DSP和FPGA的火腿肠质量检测系统设计。论文首先介绍了研究背景及意义和火腿肠质量检测系统原理，接着介绍了传统的专用和通用图像处理系统的结构、特点和模型，并通过分析DSP芯片以及DSP系统的特点，提出了基于DSP和FPGA芯片的实时图像处理系统。该系统不同于传统基于PC机模式的图像处理系统，发挥了DSP和FPGA两者的优势，能更好地提高图像处理系统实时性能。 其次,论述了以TMS320C6416 DSP为核心处理器实时图像处理系统的设计原理与组成，对系统主要部分的电路设计进行了详细的介绍，研究分析了高速电路设计中的几个关键问题。对系统进行了软件开发与调试，包括DSP程序设计和FPGA模块设计，并给出了FPGA各个模块仿真调试结果。经系统调试与实验验证，系统工作稳定可靠,拥有很高的实时性。 最后, 在火腿肠质量检测的图像算法中，对火腿肠的鼓泡问题进行了分析和相关算法的设计。首先实现了FPGA的图像预处理，将流水线处理技术和并行处理等技术应用到电路设计中，提高了处理速度，节省了硬件开销。在DSP中采用了多种算法对火腿肠图像进行了进一步的处理，使其特征更为明显。结果表明，实现的硬件电路能够满足系统功能和处理时间要求，同时有比较高的识别率，具有一定的参考价值。

Real Time Eye Tracking and Blink Detection with USB Cameras

A human-computer interface (HCI) system designed for use by people with severe disabilities is presented. People that are severely paralyzed or afflicted with diseases such as ALS (Lou Gehrig's disease) or multiple sclerosis are unable to move or control any parts of their bodies except for their eyes. The system presented here detects the user's eye blinks and analyzes the pattern and duration of the blinks, using them to provide input to the computer in the form of a mouse click. After the automatic initialization of the system occurs from the processing of the user's involuntary eye blinks in the first few seconds of use, the eye is tracked in real time using correlation with an online template. If the user's depth changes significantly or rapid head movement occurs, the system is automatically reinitialized. There are no lighting requirements nor offline templates needed for the proper functioning of the system. The system works with inexpensive USB cameras and runs at a frame rate of 30 frames per second. Extensive experiments were conducted to determine both the system's accuracy in classifying voluntary and involuntary blinks, as well as the system's fitness in varying environment conditions, such as alternative camera placements and different lighting conditions. These experiments on eight test subjects yielded an overall detection accuracy of 95.3%.

Efficient FPGA Hardware Development: A Multi-Language Approach

This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high-level hardware design and efficient hardware implementation. The central idea of this framework is the integration of different hardware languages in a way that harnesses the best features of each language. This is illustrated in this paper by the integration of two hardware languages in the form of HIDE: a structured hardware language which provides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog, and Handel-C: an ANSI C-like hardware language which allows software and hardware engineers alike to target FPGAs from high-level algorithmic descriptions. On the one hand, HIDE has proven to be very successful in the description and generation of highly optimised parameterisable FPGA circuits from geometric descriptions. On the other hand, Handel-C has also proven to be very successful in the rapid design and prototyping of FPGA circuits from algorithmic application descriptions. The proposed integrated framework hence harnesses HIDE for the generation of highly optimised circuits for regular parts of algorithms, while Handel-C is used as a top-level design language from which HIDE functionality is dynamically invoked. The overall message of this paper posits that there need not be an exclusive choice between different hardware design flows. Rather, an integrated framework where different design flows can seamlessly interoperate should be adopted. Although the idea might seem simple prima facie, it could have serious implications on the design of future generations of hardware languages.

Multidimensional DSP Core Synthesis for FPGA

This paper, chosen as a best paper from the 2004 SAMOS Workshop on Computer Systems: describes a novel, efficient methodology for automatically creating embedded DSP computer systems. The novelty arises since now embedded electronic signal processing systems, such as radar or sonar, can be designed by anyone from the algorithm level, i.e. no low level system design experience is required, whilst still achieving low controllable implementation overheads and high real time performance. In the chosen design example, a bank of Normalised Lattice Filter (NLF) components is created which a four-fold reduction in the required processing resource with no performance decrease.

Rapid Implementation and Optimisation of DSP Systems on FPGA-Centric Hetrogeneous Platforms

This paper, chosen as a best paper from the 2005 SAMOS Workshop on Computer Systems: describes the for the first time the major Abhainn project for automated system level design of embedded signal processing systems. In particular, this describes four key novelties: novel algorithm modelling techniques for DSP systems, automated implementation realisation, algorithm transformation for system optimisation and automated inter-processor communication. This is applied to two complex systems: a radar and sonar system. In both cases technology which allows non-experts to automatically create low-overhead, high performance embedded signal processing systems is exhibited.