XRD analysis of InGaN uniform layers grown on Si (111) without any buffer layers and on Sapphire

The International Workshop on Nitride Semiconductors (IWN) is a biennial academic conference in the field of group III nitride research. The IWN and the International Conference on Nitride Semiconductors (ICNS) are held in alternating years and cover similar subject areas.

Stranski-Krastanov InN/InGaN quantum dots grown directly on Si(111)

The authors discuss and demonstrate the growth of InN surface quantum dots on a high-In-content In0.73Ga0.27N layer, directly on a Si(111) substrate by plasma-assisted molecular beam epitaxy. Atomic force microscopy and transmission electron microscopy reveal uniformly distributed quantum dots with diameters of 10–40 nm, heights of 2–4 nm, and a relatively low density of ∼7 × 109 cm−2. A thin InN wetting layer below the quantum dots proves the Stranski-Krastanov growth mode. Near-field scanning optical microscopy shows distinct and spatially well localized near-infrared emission from single surface quantum dots. This holds promise for future telecommunication and sensing devices.

Lattice pulling effect and strain relaxation in axial (In, Ga)N/GaN nanowire heterostructures grown on GaN-buffered Si(111) substrate

Transmission electron microscopy and spatially resolved electron energy-loss spectroscopy have been applied to investigate the indium distribution and the interface morphology in axial (In,Ga)N/GaN nanowire heterostructures. The ordered axial (In,Ga)N/GaN nanowire heterostructures with an indium concentration up to 80% are grown by molecular beam epitaxy on GaN-buffered Si(111) substrates. We observed a pronounced lattice pulling effect in all the nanowire samples given in a broad transition region at the interface. The lattice pulling effect becomes smaller and the (In,Ga)N/GaN interface width is reduced as the indium concentration is increased in the (In,Ga)N section. The result can be interpreted in terms of the increased plastic strain relaxation via the generation of the misfit dislocations at the interface.

Electrocatalytic oxidation enhancement at the surface of InGaN films and nanostructures grown directly on Si(111)

Pronounced electrocatalytic oxidation enhancement at the surface of InGaN layers and nanostructures directly grown on Si by plasma-assisted molecular beam epitaxy is demonstrated. The oxidation enhancement, probed with the ferro/ferricyanide redox couple increases with In content and proximity of nanostructure surfaces and sidewalls to the c-plane. This is attributed to the corresponding increase of the density of intrinsic positively charged surface donors promoting electron transfer. Strongest enhancement is for c-plane InGaN layers functionalized with InN quantum dots (QDs). These results explain the excellent performance of our InN/InGaN QD biosensors and water splitting electrodes for further boosting efficiency.

An early in-situ stress signature of the AlN-Si pre-growth interface for successful integration of nitrides with (111) Si

The integration of Metal Organic Chemical Vapor Deposition (MOCVD) grown group III-A nitride device stacks on Si (111) substrates is critically dependent on the quality of the first AlN buffer layer grown. A Si surface that is both oxide-free and smooth is a primary requirement for nucleating such layers. A single parameter, the AlN layer growth stress, is shown to be an early (within 50 nm), clear (<0.5 GPa versus > 1GPa), and fail-safe indicator of the pre-growth surface, and the AlN quality required for successful epitaxy. Grain coalescence model for stress generation is used to correlate growth stress, the AlN-Si interface, and crystal quality. (C) 2013 AIP Publishing LLC.

Customizing electron confinement in plasma-assembled Si/AlN nanodots for solar cell applications

Size-uniform Si nanodots (NDs) are synthesized on an AlN buffer layer at low Si(111) substrate temperatures using inductively coupled plasma-assisted magnetron sputtering deposition. High-resolution electron microscopy reveals that the sizes of the Si NDs range from 9 to 30 nm. Room-temperature photoluminescence (PL) spectra indicate that the energy peak shifts from 738 to 778 nm with increasing the ND size. In this system, the quantum confinement effect is fairly strong even for relatively large (up to 25 nm in diameter) NDs, which is promising for the development of the next-generation all-Si tandem solar cells capable of effectively capturing sunlight photons with the energies between 1.7 (infrared: large NDs) and 3.4 eV (ultraviolet: small NDs). The strength of the resulting electron confinement in the Si/AlN ND system is evaluated and justified by analyzing the measured PL spectra using the ionization energy theory approximation.

Temperature dependent transport studies in InN quantum dots grown by droplet epitaxy on silicon nitride/Si substrate

InN quantum dots (QDs) were fabricated on silicon nitride/Si (111) substrate by droplet epitaxy. Single-crystalline structure of InN QDs was verified by transmission electron microscopy, and the chemical bonding configurations of InN QDs were examined by x-ray photoelectron spectroscopy. Photoluminescence measurement shows a slight blue shift compared to the bulk InN, arising from size dependent quantum confinement effect. The interdigitated electrode pattern was created and current-voltage (I-V) characteristics of InN QDs were studied in a metal-semiconductor-metal configuration in the temperature range of 80-300K. The I-V characteristics of lateral grown InN QDs were explained by using the trap model. (C) 2011 American Institute of Physics. [doi:10.1063/1.3651762]

Band-Structure Lineup at In0.2Ga0.8N/Si Heterostructures by X-ray Photoelectron Spectroscopy

In0.2Ga0.8N layers were directly grown on Si(111) substrate by plasma-assisted molecular beam epitaxy (PAMBE). Structural characteristics of the as-grown InGaN epilayers were evaluated high resolution X-ray diffraction and composition of InGaN was estimated from photoluminescence spectra using the standard Vegard's law. High-resolution X-ray photoemission spectroscopy measurements were used to determine the band offset of wurtzite-In0.2Ga0.8N/Si(111) heterojunctions. The valence band of InGaN is found to be 2.08 +/- 0.04 eV below that of Si. The conduction band offset (CBO) of InGaN/Si heterojunction is found similar to 0.74 eV and a type-II heterojunction. (C) 2012 The Japan Society of Applied Physics

Trap modulated photoresponse of InGaN/Si isotype heterojunction at zero-bias

n-n isotype heterojunction of InGaN and bare Si (111) was formed by plasma assisted molecular beam epitaxy without nitridation steps or buffer layers. High resolution X-ray diffraction studies were carried out to confirm the formation of epilayers on Si (111). X-ray rocking curves revealed the presence of large number of edge threading dislocations at the interface. Room temperature photoluminescence studies were carried out to confirm the bandgap and the presence of defects. Temperature dependent I-V measurements of Al/InGaN/Si (111)/Al taken in dark confirm the rectifying nature of the device. I-V characteristics under UV illumination, showed modest rectification and was operated at zero bias making it a self-powered device. A band diagram of the heterojunction is proposed to understand the transport mechanism for self-powered functioning of the device. (c) 2015 AIP Publishing LLC.

Taper-free and vertically oriented Ge nanowires on Ge/Si substrates grown by a two-temperature process

Taper-free and vertically oriented Ge nanowires were grown on Si (111) substrates by chemical vapor deposition with Au nanoparticle catalysts. To achieve vertical nanowire growth on the highly lattice mismatched Si substrate, a thin Ge buffer layer was first deposited, and to achieve taper-free nanowire growth, a two-temperature process was employed. The two-temperature process consisted of a brief initial base growth step at high temperature followed by prolonged growth at lower temperature. Taper-free and defect-free Ge nanowires grew successfully even at 270 °C, which is 90 °C lower than the bulk eutectic temperature. The yield of vertical and taper-free nanowires is over 90%, comparable to that of vertical but tapered nanowires grown by the conventional one-temperature process. This method is of practical importance and can be reliably used to develop novel nanowire-based devices on relatively cheap Si substrates. Additionally, we observed that the activation energy of Ge nanowire growth by the two-temperature process is dependent on Au nanoparticle size. The low activation energy (∼5 kcal/mol) for 30 and 50 nm diameter Au nanoparticles suggests that the decomposition of gaseous species on the catalytic Au surface is a rate-limiting step. A higher activation energy (∼14 kcal/mol) was determined for 100 nm diameter Au nanoparticles which suggests that larger Au nanoparticles are partially solidified and that growth kinetics become the rate-limiting step. © 2011 American Chemical Society.

Defect-free GaAs/AlGaAs Core-shell nanowires on Si substrates

We report straight and vertically aligned defect-free GaAs nanowires grown on Si(111) substrates by metal-organic chemical vapor deposition. By deposition of thin GaAs buffer layers on Si substrates, these nanowires could be grown on the buffer layers with much less stringent conditions as otherwise imposed by epitaxy of III-V compounds on Si. Also, crystal-defect-free GaAs nanowires were grown by using either a two-temperature growth mode consisting of a short initial nucleation step under higher temperature followed by subsequent growth under lower temperature or a rapid growth rate mode with high source flow rate. These two growth modes not only eliminated planar crystallographic defects but also significantly reduced tapering. Core-shell GaAs-AlGaAs nanowires grown by the two-temperature growth mode showed improved optical properties with strong photoluminescence and long carrier life times. © 2011 American Chemical Society.

Structural and optical characterization of vertical GaAs/GaP core-shell nanowires grown on Si substrates

GaAs nanowires were grown on Si (111) substrates. By coating a thin GaAs buffer layer on Si surface and using a two-temperature growth, the morphology and crystal structure of GaAs nanowires were dramatically improved. The strained GaAs/GaP core-shell nanowires, based on the improved GaAs nanowires with a shell thickness of 25 nm, showed a significant shift in emission energy of 260 meV from the unstrained GaAs nanowires. © 2010 IEEE.

Novel growth and properties of GaAs nanowires on Si substrates.

Straight, vertically aligned GaAs nanowires were grown on Si(111) substrates coated with thin GaAs buffer layers. We find that the V/III precursor ratio and growth temperature are crucial factors influencing the morphology and quality of buffer layers. A double layer structure, consisting of a thin initial layer grown at low V/III ratio and low temperature followed by a layer grown at high V/III ratio and high temperature, is crucial for achieving straight, vertically aligned GaAs nanowires on Si(111) substrates. An in situ annealing step at high temperature after buffer layer growth improves the surface and structural properties of the buffer layer, which further improves the morphology of the GaAs nanowire growth. Through such optimizations we show that vertically aligned GaAs nanowires can be fabricated on Si(111) substrates and achieve the same structural and optical properties as GaAs nanowires grown directly on GaAs(111)B substrates.

Improvement of morphology, structure, and optical properties of GaAs nanowires grown on Si substrates

We investigate vertical and defect-free growth of GaAs nanowires on Si (111) substrates via a vapor-liquid-solid (VLS) growth mechanism with Au catalysts by metal-organic chemical vapor deposition (MOCVD). By using annealed thin GaAs buffer layers on the surface of Si substrates, most nanowires are grown on the substrates straight, following (111) direction; by using two temperature growth, the nanowires were grown free from structural defects, such as twin defects and stacking faults. Systematic experiments about buffer layers indicate that V/III ratio of precursor and growth temperature can affect the morphology and quality of the buffer layers. Especially, heterostructural buffer layers grown with different V/III ratios and temperatures and in-situ post-annealing step are very helpful to grow well arranged, vertical GaAs nanowires on Si substrates. The initial nanowires having some structural defects can be defect-free by two-temperature growth mode with improved optical property, which shows us positive possibility for optoelectronic device application. ©2010 IEEE.

Low-cost high-efficiency GaN LED on large-area si substrate

The use of large size Si substrates for epitaxy of nitride light emitting diode (LED) structures has attracted great interest because Si wafers are readily available in large diameter at low cost. In addition, such wafers are compatible with existing processing lines for the 6-inch and larger wafer sizes commonly used in the electronics industry. With the development of various methods to avoid wafer cracking and reduce the defect density, the performance of GaN-based LED and electronic devices has been greatly improved. In this paper, we review our methods of growing crack-free InGaN-GaN multiple quantum well (MQW) LED structures of high crystalline quality on Si(111) substrates. The performance of processed LED devices and its dependence on the threading dislocation density were studied. Full wafer-level LED processing using a conventional 6-inch III-V processing line is also presented, demonstrating the great advantage of using large-size Si substrates for mass production of GaN LED devices.