965 resultados para Pulse techniques (Electronics)


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Two simple methods for estimating the potential modulation bandwidth of TO packaging technique are presented. The first method is based upon the comparison of the measured frequency responses of the laser diodes and the TO laser modules, and the second is from the equivalent circuit for the test fixture, the TO header, the submount and the bonding wire. It is shown that the TO packaging techniques used in the experiments can potentially achieve a frequency bandwidth of over 10.5 GHz, and the two proposed methods give similar results.

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Scattering parameters of photodiode chip, TO header and TO packaged module are measured, and the effects of TO packaging network on the high-frequency response of photodiode are investigated. Based on the analysis, the potential bandwidth of TO packaging techniques is estimated from the scattering parameters of the TO packaging network. Another method for estimating the potential bandwidth from the equivalent circuit for the TO packaged photodiode model is also presented. The results obtained using both methods show that the TO packaging techniques used in the experiments can potentially achieve a frequency bandwidth of 22 GHz.

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Current-based microscopic defect analysis method such as current deep level transient spectroscopy (I-DLTS) and thermally stimulated current have been developed over the years at Brookhaven National Laboratory (BNL) for the defect characterizations on heavily irradiated (Phi(n) >= 10(13) n/cm(2)) high-resistivity (>= 2 k Omega cm) Si sensors/detectors. The conventional DLTS method using a capacitance transient is not valid on heavily irradiated high-resistivity Si sensors/detectors. A new optical filling method, using lasers with various wavelengths, has been applied, which is more efficient and suitable than the traditional voltage-pulse filling. Optimum defect-filling schemes and conditions have been suggested for heavily irradiated high-resistivity Si sensors/detectors. (c) 2006 Published by Elsevier Ltd.

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Low-temperature-grown GaAs (LT-GaAs) of 1-um thickness was grown at 250 degrees C on semi-insulating GaAs (001) substrate using EPI GEN-II solid-source MBE system. The sample was then in situ annealed for 10 min at 600 degrees C under As-rich condition. THz emitters were fabricated on this LTGaAs with three different photoconductive dipole antenna gaps of 1-mm, 3-mm, and 5-mm, respectively. The spectral bandwidth of 2.75 THz was obtaind with time domain spectroscopy. It is found that THz emission efficiency is increased with decreasing antenna gap. Two carrier lifetimes, 0.469 ps and 3.759 ps, were obtained with time-resolved transient reflection-type pump-probe spectroscopy.

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Current-based microscopic defect analysis method such as current deep level transient spectroscopy (I-DLTS) and thermally stimulated current have been developed over the years at Brookhaven National Laboratory (BNL) for the defect characterizations on heavily irradiated (Phi(n) >= 10(13) n/cm(2)) high-resistivity (>= 2 k Omega cm) Si sensors/detectors. The conventional DLTS method using a capacitance transient is not valid on heavily irradiated high-resistivity Si sensors/detectors. A new optical filling method, using lasers with various wavelengths, has been applied, which is more efficient and suitable than the traditional voltage-pulse filling. Optimum defect-filling schemes and conditions have been suggested for heavily irradiated high-resistivity Si sensors/detectors. (c) 2006 Published by Elsevier Ltd.

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Current based microscopic defect analysis methods such as current deep level transient spectroscopy (I-DLTS) and thermally stimulated current (TSC) have been further developed in accordance with the need for the defect analysis of highly irradiated (Phi(n) > 10(13) n/cm(2)) high resistivity silicon detectors. The new I-DLTS/TSC system has a temperature range of 8 K less than or equal to T less than or equal to 450 K and a high sensitivity that can detect a defect concentration of less than 10(10)/cm(3) (background noise as low as 10 fA). A new filling method using different wavelength laser illumination has been applied, which is more efficient and suitable than the traditional voltage pulse filling. It has been found that the filling of a defect level depends on such factors as the total concentration of free carriers generated or injected, the penetration length of the laser (laser wavelength), the temperature at which the filling is taking place, as well as the decay time after the filling (but before the measurement). The mechanism of the defect filling can be explained by the competition between trapping and detrapping of defect levels, possible capture cross section temperature dependence, and interaction among various defect levels in terms of charge transferring. Optimum defect filling conditions have been suggested for highly irradiated high resistivity silicon detectors.

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We present an efficient method to generate a ultrashort attosecond (as) pulse when a model He+ ion is exposed to the combination of an intense few-cycle chirped laser pulse and its 27th harmonics. By solving the time-dependent Schroumldinger equation, we found that high-order harmonic generation (HHG) from He+ ion is enhanced by seven orders of magnitude due to the presence of the harmonic pulse. After optimizing the chirp of the fundamental pulse, we show that the cut-off energy of the generated harmonics is extended effectively to I-p+25.5U(p). As a result, an isolated 26-as pulse with a bandwidth of 170.5 eV can be obtained directly from the supercontinuum around the cut-off of HHG. To better understand the physical origin of HHG enhancement and attosecond pulse emission, we perform semiclassical simulations and analyze the time-frequency characteristics of attosecond pulse.

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High-permittivity ("high-k") dielectric materials are used in the transistor gate stack in integrated circuits. As the thickness of silicon oxide dielectric reduces below 2 nm with continued downscaling, the leakage current because of tunnelling increases, leading to high power consumption and reduced device reliability. Hence, research concentrates on finding materials with high dielectric constant that can be easily integrated into a manufacturing process and show the desired properties as a thin film. Atomic layer deposition (ALD) is used practically to deposit high-k materials like HfO2, ZrO2, and Al2O3 as gate oxides. ALD is a technique for producing conformal layers of material with nanometer-scale thickness, used commercially in non-planar electronics and increasingly in other areas of science and technology. ALD is a type of chemical vapor deposition that depends on self-limiting surface chemistry. In ALD, gaseous precursors are allowed individually into the reactor chamber in alternating pulses. Between each pulse, inert gas is admitted to prevent gas phase reactions. This thesis provides a profound understanding of the ALD of oxides such as HfO2, showing how the chemistry affects the properties of the deposited film. Using multi-scale modelling of ALD, the kinetics of reactions at the growing surface is connected to experimental data. In this thesis, we use density functional theory (DFT) method to simulate more realistic models for the growth of HfO2 from Hf(N(CH3)2)4/H2O and HfCl4/H2O and for Al2O3 from Al(CH3)3/H2O.Three major breakthroughs are discovered. First, a new reaction pathway, ’multiple proton diffusion’, is proposed for the growth of HfO2 from Hf(N(CH3)2)4/H2O.1 As a second major breakthrough, a ’cooperative’ action between adsorbed precursors is shown to play an important role in ALD. By this we mean that previously-inert fragments can become reactive once sufficient molecules adsorb in their neighbourhood during either precursor pulse. As a third breakthrough, the ALD of HfO2 from Hf(N(CH3)2)4 and H2O is implemented for the first time into 3D on-lattice kinetic Monte-Carlo (KMC).2 In this integrated approach (DFT+KMC), retaining the accuracy of the atomistic model in the higher-scale model leads to remarkable breakthroughs in our understanding. The resulting atomistic model allows direct comparison with experimental techniques such as X-ray photoelectron spectroscopy and quartz crystal microbalance.

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In the last decade, we have witnessed the emergence of large, warehouse-scale data centres which have enabled new internet-based software applications such as cloud computing, search engines, social media, e-government etc. Such data centres consist of large collections of servers interconnected using short-reach (reach up to a few hundred meters) optical interconnect. Today, transceivers for these applications achieve up to 100Gb/s by multiplexing 10x 10Gb/s or 4x 25Gb/s channels. In the near future however, data centre operators have expressed a need for optical links which can support 400Gb/s up to 1Tb/s. The crucial challenge is to achieve this in the same footprint (same transceiver module) and with similar power consumption as today’s technology. Straightforward scaling of the currently used space or wavelength division multiplexing may be difficult to achieve: indeed a 1Tb/s transceiver would require integration of 40 VCSELs (vertical cavity surface emitting laser diode, widely used for short‐reach optical interconnect), 40 photodiodes and the electronics operating at 25Gb/s in the same module as today’s 100Gb/s transceiver. Pushing the bit rate on such links beyond today’s commercially available 100Gb/s/fibre will require new generations of VCSELs and their driver and receiver electronics. This work looks into a number of state‐of-the-art technologies and investigates their performance restraints and recommends different set of designs, specifically targeting multilevel modulation formats. Several methods to extend the bandwidth using deep submicron (65nm and 28nm) CMOS technology are explored in this work, while also maintaining a focus upon reducing power consumption and chip area. The techniques used were pre-emphasis in rising and falling edges of the signal and bandwidth extensions by inductive peaking and different local feedback techniques. These techniques have been applied to a transmitter and receiver developed for advanced modulation formats such as PAM-4 (4 level pulse amplitude modulation). Such modulation format can increase the throughput per individual channel, which helps to overcome the challenges mentioned above to realize 400Gb/s to 1Tb/s transceivers.

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The future of many companies will depend to a large extent on their ability to initiate techniques that bring schedules, performance, tests, support, production, life-cycle-costs, reliability prediction and quality control into the earliest stages of the product creation process. Important questions for an engineer who is responsible for the quality of electronic parts such as printed circuit boards (PCBs) during design, production, assembly and after-sales support are: What is the impact of temperature? What is the impact of this temperature on the stress produced in the components? What is the electromagnetic compatibility (EMC) associated with such a design? At present, thermal, stress and EMC calculations are undertaken using different software tools that each require model build and meshing. This leads to a large investment in time, and hence cost, to undertake each of these simulations. This paper discusses the progression towards a fully integrated software environment, based on a common data model and user interface, having the capability to predict temperature, stress and EMC fields in a coupled manner. Such a modelling environment used early within the design stage of an electronic product will provide engineers with fast solutions to questions regarding thermal, stress and EMC issues. The paper concentrates on recent developments in creating such an integrated modeling environment with preliminary results from the analyses conducted. Further research into the thermal and stress related aspects of the paper is being conducted under a nationally funded project, while their application in reliability prediction will be addressed in a new European project called PROFIT.

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The future success of many electronics companies will depend to a large extent on their ability to initiate techniques that bring schedules, performance, tests, support, production, life-cycle-costs, reliability prediction and quality control into the earliest stages of the product creation process. Earlier papers have discussed the benefits of an integrated analysis environment for system-level thermal, stress and EMC prediction. This paper focuses on developments made to the stress analysis module and presents results obtained for an SMT resistor. Lifetime predictions are made using the Coffin-Manson equation. Comparison with the creep strain energy based models of Darveaux (1997) shows the shear strain based method to underestimate the solder joint life. Conclusions are also made about the capabilities of both approaches to predict the qualitative and quantitative impact of design changes.

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This paper describes modeling technology and its use in providing data governing the assembly and subsequent reliability of electronic chip components on printed circuit boards (PCBs). Products, such as mobile phones, camcorders, intelligent displays, etc., are changing at a tremendous rate where newer technologies are being applied to satisfy the demands for smaller products with increased functionality. At ever decreasing dimensions, and increasing number of input/output connections, the design of these components, in terms of dimensions and materials used, is playing a key role in determining the reliability of the final assembly. Multiphysics modeling techniques are being adopted to predict a range of interacting physics-based phenomena associated with the manufacturing process. For example, heat transfer, solidification, marangoni fluid flow, void movement, and thermal-stress. The modeling techniques used are based on finite volume methods that are conservative and take advantage of being able to represent the physical domain using an unstructured mesh. These techniques are also used to provide data on thermal induced fatigue which is then mapped into product lifetime predictions.

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This paper presents innovative work in the development of policy-based autonomic computing. The core of the work is a powerful and flexible policy-expression language AGILE, which facilitates run-time adaptable policy configuration of autonomic systems. AGILE also serves as an integrating platform for other self-management technologies including signal processing, automated trend analysis and utility functions. Each of these technologies has specific advantages and applicability to different types of dynamic adaptation. The AGILE platform enables seamless interoperability of the different technologies to each perform various aspects of self-management within a single application. The various technologies are implemented as object components. Self-management behaviour is specified using the policy language semantics to bind the various components together as required. Since the policy semantics support run-time re-configuration, the self-management architecture is dynamically composable. Additional benefits include the standardisation of the application programmer interface, terminology and semantics, and only a single point of embedding is required.

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This paper discusses the reliability of power electronics modules. The approach taken combines numerical modeling techniques with experimentation and accelerated testing to identify failure modes and mechanisms for the power module structure and most importantly the root cause of a potential failure. The paper details results for two types of failure (i) wire bond fatigue and (ii) substrate delamination. Finite element method modeling techniques have been used to predict the stress distribution within the module structures. A response surface optimisation approach has been employed to enable the optimal design and parameter sensitivity to be determined. The response surface is used by a Monte Carlo method to determine the effects of uncertainty in the design.

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In this paper, a method for the integration of several numerical analytical techniques that are used in microsystems design and failure analysis is presented. The analytical techniques are categorized into four groups in the discussion, namely the high-fidelity analytical tools, i.e. finite element (FE) method, the fast analytical tools referring to reduced order modeling (ROM); the optimization tools, and probability based analytical tools. The characteristics of these four tools are investigated. The interactions between the four tools are discussed and a methodology for the coupling of these four tools is offered. This methodology consists of three stages, namely reduced order modeling, deterministic optimization and probabilistic optimization. Using this methodology, a case study for optimization of a solder joint is conducted. It is shown that these analysis techniques have mutual relationship of interaction and complementation. Synthetic application of these techniques can fully utilize the advantages of these techniques and satisfy various design requirements. The case study shows that the coupling method of different tools provided by this paper is effective and efficient and it is highly relevant in the design and reliability analysis of microsystems