Low-Frequency Noise in Field-Effect Devices Functionalized With Dendrimer/Carbon-Nanotube Multilayers

Low-frequency noise in an electrolyte-insulator- semiconductor (EIS) structure functionalized with multilayers of polyamidoamine (PAMAM) dendrimer and single-walled carbon nanotubes (SWNT) is studied. The noise spectral density exhibits 1/f(gamma) dependence with the power factor of gamma approximate to 0.8 and gamma = 0.8-1.8 for the bare and functionalized EIS sensor, respectively. The gate-voltage noise spectral density is practically independent of the pH value of the solution and increases with increasing gate voltage or gate-leakage current. It has been revealed that functionalization of an EIS structure with a PAMAM/SWNTs multilayer leads to an essential reduction of the 1/f noise. To interpret the noise behavior in bare and functionalized EIS devices, a gate-current noise model for capacitive EIS structures based on an equivalent flatband-voltage fluctuation concept has been developed.

HOW TO EFFICIEN TLY INCORPORATE FACTS DEVICES IN OPTIMAL ACTIVE POWER FLOW MODEL

This paper presents for the first time how to easily incorporate facts devices in an optimal active power flow model such that an efficient interior-point method may be applied. The optimal active power flow model is based on a network flow approach instead of the traditional nodal formulation that allows the use of an efficiently predictor-corrector interior point method speed up by sparsity exploitation. The mathematical equivalence between the network flow and the nodal models is addressed, as well as the computational advantages of the former considering the solution by interior point methods. The adequacy of the network flow model for representing facts devices is presented and illustrated on a small 5-bus system. The model was implemented using Matlab and its performance was evaluated with the 3,397-bus and 4,075-branch Brazilian power system which show the robustness and efficiency of the formulation proposed. The numerical results also indicate an efficient tool for optimal active power flow that is suitable for incorporating facts devices.

Technology assessment for power quality mitigation devices - Micro-DVR case study

This work presents a case study on technology assessment for power quality improvement devices. A system compatibility test protocol for power quality mitigation devices was developed in order to evaluate the functionality of three-phase voltage restoration devices. In order to validate this test protocol, the micro-DVR, a reduced power development platform for DVR (dynamic voltage restorer) devices, was tested and the results are discussed based on voltage disturbances standards. (C) 2011 Elsevier B.V. All rights reserved.

Electrical Power Distribution System modeling with VHDL-AMS for the construction of a Real-Time Digital Simulator using FPGAS devices

This paper presents a distribution feeder simulation using VHDL-AMS, considering the standard IEEE 13 node test feeder admitted as an example. In an electronic spreadsheet all calculations are performed in order to develop the modeling in VHDL-AMS. The simulation results are compared in relation to the results from the well knowing MatLab/Simulink environment, in order to verify the feasibility of the VHDL-AMS modeling for a standard electrical distribution feeder, using the software SystemVision™. This paper aims to present the first major developments for a future Real-Time Digital Simulator applied to Electrical Power Distribution Systems. © 2012 IEEE.

Effects of time exposure and low power sonochemical treatment on ZnO mesostructures

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Dynamic power management: from portable devices to high performance computing

Electronic applications are nowadays converging under the umbrella of the cloud computing vision. The future ecosystem of information and communication technology is going to integrate clouds of portable clients and embedded devices exchanging information, through the internet layer, with processing clusters of servers, data-centers and high performance computing systems. Even thus the whole society is waiting to embrace this revolution, there is a backside of the story. Portable devices require battery to work far from the power plugs and their storage capacity does not scale as the increasing power requirement does. At the other end processing clusters, such as data-centers and server farms, are build upon the integration of thousands multiprocessors. For each of them during the last decade the technology scaling has produced a dramatic increase in power density with significant spatial and temporal variability. This leads to power and temperature hot-spots, which may cause non-uniform ageing and accelerated chip failure. Nonetheless all the heat removed from the silicon translates in high cooling costs. Moreover trend in ICT carbon footprint shows that run-time power consumption of the all spectrum of devices accounts for a significant slice of entire world carbon emissions. This thesis work embrace the full ICT ecosystem and dynamic power consumption concerns by describing a set of new and promising system levels resource management techniques to reduce the power consumption and related issues for two corner cases: Mobile Devices and High Performance Computing.

Power Transient Analysis of Experimental Devices for Jules Horowitz Material Testing Reactor (JHR)

The objective of this thesis is the power transient analysis concerning experimental devices placed within the reflector of Jules Horowitz Reactor (JHR). Since JHR material testing facility is designed to achieve 100 MW core thermal power, a large reflector hosts fissile material samples that are irradiated up to total relevant power of 3 MW. MADISON devices are expected to attain 130 kW, conversely ADELINE nominal power is of some 60 kW. In addition, MOLFI test samples are envisaged to reach 360 kW for what concerns LEU configuration and up to 650 kW according to HEU frame. Safety issues concern shutdown transients and need particular verifications about thermal power decreasing of these fissile samples with respect to core kinetics, as far as single device reactivity determination is concerned. Calculation model is conceived and applied in order to properly account for different nuclear heating processes and relative time-dependent features of device transients. An innovative methodology is carried out since flux shape modification during control rod insertions is investigated regarding the impact on device power through core-reflector coupling coefficients. In fact, previous methods considering only nominal core-reflector parameters are then improved. Moreover, delayed emissions effect is evaluated about spatial impact on devices of a diffuse in-core delayed neutron source. Delayed gammas transport related to fission products concentration is taken into account through evolution calculations of different fuel compositions in equilibrium cycle. Provided accurate device reactivity control, power transients are then computed for every sample according to envisaged shutdown procedures. Results obtained in this study are aimed at design feedback and reactor management optimization by JHR project team. Moreover, Safety Report is intended to utilize present analysis for improved device characterization.

Towards End-User Driven Power Saving Control in Android devices

Abstract. During the last decade mobile communications increasingly became part of people's daily routine. Such usage raises new challenges regarding devices' battery lifetime management when using most popular wireless access technologies, such as IEEE 802.11. This paper investigates the energy/delay trade-off of using an end-user driven power saving approach, when compared with the standard IEEE 802.11 power saving algorithms. The assessment was conducted in a real testbed using an Android mobile phone and high-precision energy measurement hardware. The results show clear energy benefits of employing user-driven power saving techniques, when compared with other standard approaches.

Power Measurement Methodology for FPGA Devices

The efficiency of power optimization tools depends on information on design power provided by the power estimation models. Power models targeting different power groups can enable fast identification of the most power consuming parts of design and their properties. The accuracy of these estimation models is highly dependent on the accuracy of the method used for their characterization. The highest precision is achieved by using physical onboard measurements. In this paper, we present a measurement methodology that is primarily aimed at calibrating and validating high-level dynamic power estimation models. The measurements have been carefully designed to enable the separation of the interconnect power from the logic power and the power of the clock circuitry, so that each of these power groups can be used for the corresponding model validation. The standard measurement uncertainty is lower than 2% of the measured value even with a very small number of repeated measurements. Additionally, the accuracy of a commercial low-level power estimation tool has been also assessed for comparison purposes. The results indicate that the tool is not suitable for power estimation of data path-oriented designs.

Modeling Reflective Bistability in Vertical-Cavity Semiconductor Optical Amplifiers

The characteristics of optical bistability in a vertical- cavity semiconductor optical amplifier (VCSOA) operated in reflection are reported. The dependences of the optical bistability in VCSOAs on the initial phase detuning and on the applied bias current are analyzed. The optical bistability is also studied for different numbers of superimposed periods in the top distributed bragg reflector (DBR) that conform the internal cavity of the device. The appearance of the X-bistable and the clockwise bistable loops is predicted theoretically in a VCSOA operated in reflection for the first time, to the best of our knowledge. Moreover, it is also predicted that the control of the VCSOA’s top reflectivity by the addition of new superimposed periods in its top DBR reduces by one order of magnitude the input power needed for the assessment of the X- and the clockwise bistable loop, compared to that required in in-plane semiconductor optical amplifiers. These results, added to the ease of fabricating two-dimensional arrays of this kind of device could be useful for the development of new optical logic or optical signal regeneration devices.

Wavelength monitoring with semiconductor laser amplifiers

The semiconductor laser diodes that are typically used in applications of optical communications, when working as amplifiers, present under certain conditions optical bistability, which is characterized by abruptly switching between two different output states and an associated hysteresis cycle. This bistable behavior is strongly dependent on the frequency detuning between the frequency of the external optical signal that is injected into the semiconductor laser amplifier and its own emission frequency. This means that small changes in the wavelength of an optical signal applied to a laser amplifier causes relevant changes in the characteristics of its transfer function in terms of the power requirements to achieve bistability and the width of the hysteresis. This strong dependence in the working characteristics of semiconductor laser amplifiers on frequency detuning suggest the use of this kind of devices in optical sensing applications for optical communications, such as the detection of shifts in the emission wavelength of a laser, or detect possible interference between adjacent channels in DWDM (Dense Wavelength Division Multiplexing) optical communication networks

Vertical-cavity semiconductor optical amplifiers (VCSOAs) as optical sensing elements

Semiconductor Optical Amplifiers (SOAs) have mainly found application in optical telecommunication networks for optical signal regeneration, wavelength switching or wavelength conversion. The objective of this paper is to report the use of semiconductor optical amplifiers for optical sensing taking into account their optical bistable properties. As it was previously reported, some semiconductor optical amplifiers, including Fabry-Perot and Distributed-Feedback Semiconductor Optical Amplifiers (FPSOAs and DFBSOAs), may exhibit optical bistability. The characteristics of the attained optical bistability in this kind of devices are strongly dependent on different parameters including wavelength, temperature or applied bias current and small variations lead to a change on their bistable properties. As in previous analyses for Fabry-Perot and DFB SOAs, the variations of these parameters and their possible application for optical sensing are reported in this paper for the case of the Vertical-Cavity Semiconductor Optical Amplifier (VCSOA). When using a VCSOA, the input power needed for the appearance of optical bistability is one order of magnitude lower than that needed in edge-emitting devices. This feature, added to the low manufacturing costs of VCSOAs and the ease to integrate them in 2-D arrays, makes the VCSOA a very promising device for its potential use in optical sensing applications.

Low-power vertical cavity NAND gate

The study of the Vertical-Cavity Semiconductor Optical Amplifiers (VCSOAs) for optical signal processing applications is increasing his interest. Due to their particular structure, the VCSOAs present some advantages when compared to their edge-emitting counterparts including low manufacturing costs, high coupling efficiency to optical fibers and the ease to fabricate 2-D arrays of this kind of devices. As a consequence, all-optical logic gates based on VCSOAs may be very promising devices for their use in optical computing and optical switching in communications. Moreover, since all the boolean logic functions can be implemented by combining NAND logic gates, the development of a Vertical-Cavity NAND gate would be of particular interest. In this paper, the characteristics of the dispersive optical bistability appearing on a VCSOA operated in reflection are studied. A progressive increment of the number of layers compounding the top Distributed Bragg Reflector (DBR) of the VCSOA results on a change on the shape of the appearing bistability from an S-shape to a clockwise bistable loop. This resulting clockwise bistability has high on-off contrast ratio and input power requirements one order of magnitude lower than those needed for edge-emitting devices. Based on these results, an all-optical vertical-cavity NAND gate with high on-off contrast ratio and an input power for operation of only 10|i\V will be reported in this paper.

Simulation and geometrical design of multi-section tapered semiconductor optical amplifiers at 1.57 µm

Fully integrated semiconductor master-oscillator power-amplifiers (MOPA) with a tapered power amplifier are attractive sources for applications requiring high brightness. The geometrical design of the tapered amplifier is crucial to achieve the required power and beam quality. In this work we investigate by numerical simulation the role of the geometrical design in the beam quality and in the maximum achievable power. The simulations were performed with a Quasi-3D model which solves the complete steady-state semiconductor and thermal equations combined with a beam propagation method. The results indicate that large devices with wide taper angles produce higher power with better beam quality than smaller area designs, but at expenses of a higher injection current and lower conversion efficiency.