986 resultados para Metal insulator semiconductors


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In celebrating Professor C. N. R. Rao's 80th birthday, this article recalls his singular contributions to solid state and materials chemistry for about sixty years. In so doing, the article also traces the growth of the field as a central domain of research in chemical sciences from its early origins in Europe. Although Rao's major work lies in solid state and materials chemistry - a field which he started and nurtured in India while its importance was being recognized internationally - his contributions to other areas of chemistry (and physics), viz., molecular spectroscopy, phase transitions, fullerenes, graphene, nanomaterials and multiferroics are equally significant. Illustrative examples of his work devoted to rare earth and transition metal oxides, defects and nonstoichiometry, metal-insulator transitions, investigation of crystal and electronic structures of a variety of solids by means of electron microscopies and photoelectron spectroscopy, superconducting cuprates, magnetoresistive manganites, multiferroic metal oxides of various structures and, last but not the least, development of new strategies for chemical synthesis of a wide variety of solids including nanomaterials and framework solids in different dimensionalities, are highlighted. The article also captures his exemplary role as a science teacher, science educationist and institution builder in post-Independence India.

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Titanium dioxide (TiO2) thin films were deposited onto p-Si substrates held at room temperature by reactive Direct Current (DC) magnetron sputtering at various sputter powers in the range 80-200W. The as-deposited TiO2 films were annealed at a temperature of 1023K. The post-annealed films were characterized for crystallographic structure, chemical binding configuration, surface morphology and optical absorption. The electrical and dielectric properties of Al/TiO2/p-Si structure were determined from the capacitance-voltage and current-voltage characteristics. X-ray diffraction studies confirmed that the as-deposited films were amorphous in nature. After post-annealing at 1023K, the films formed at lower powers exhibited anatase phase, where as those deposited at sputter powers >160W showed the mixed anatase and rutile phases of TiO2. The surface morphology of the films varied significantly with the increase of sputter power. The electrical and dielectric properties on the air-annealed Al/TiO2/p-Si structures were studied. The effect of sputter power on the electrical and dielectric characteristics of the structure of Al/TiO2/p-Si (metal-insulator-semiconductor) was systematically investigated. Copyright (c) 2014 John Wiley & Sons, Ltd.

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We report the room temperature fabrication of Ta/TiO2/Ta metal-insulator-metal (MIM) capacitors (mainly, for DRAM applications). The fabricated devices show high capacitance density (similar to 15 fF/mu m(2)), and low leakage current density of 6.4 X 10(-8) A/cm(2) (27 degrees C) and 3.3 x 10(-6) A/cm(2) (125 degrees C) at -1 V. We analyze the electrical and material characteristics of the fabricated capacitors, and compare the device performance of these capacitors with other TiO2 and TiO2-based MIM capacitors reported in recent literature.

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We demonstrate the growth of high quality single phase films of VO2(A, B, and M) on SrTiO3 substrate by controlling the vanadium arrival rate (laser frequency) and oxidation of the V atoms. A phase diagram has been developed (oxygen pressure versus laser frequency) for various phases of VO2 and their electronic properties are investigated. VO2(A) phase is insulating VO2(B) phase is semi-metallic, and VO2(M) phase exhibits a metal-insulator transition, corroborated by photoelectron spectroscopic studies. The ability to control the growth of various polymorphs opens up the possibility for novel (hetero) structures promising new device functionalities. (C) 2015 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution 3.0 Unported License.

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Vanadium Oxide has been a frontrunner in the field of oxide electronics because of its metal-insulator transition (MIT). The interplay of different structures of VO2 has played a crucial role in deciding the magnitude of the first order MIT. Substitution doping has been found to introduce different polymorphs of VO2. Hence the role of substitution doping in stabilizing the competing phases of VO2 in the thin film form remains underexplored. Consequently there have been reports both discounting and approving such a stabilization of competing phases in VO2. It is reported in the literature that the bandwidth of the hysteresis and transition temperature of VO2 can be tuned by substitutional doping of VO2 with W. In this work, we have adopted a novel technique called, Ultrasonic Nebulized Spray Pyrolysis of Aqueous Combustion Mixture (UNSPACM) to deposit VO2 and W- doped VO2 as thin films. XRD and Raman spectroscopy were used to investigate the role of tungsten on the structure of VO2 thin films. Morphology of the thin films was found to be consisting of globular and porous nanoparticles of size similar to 20nm. Transition temperature decreased with the addition of W. We found that for 2.0 at % W doping in VO2, the transition temperature has reduced from 68 degrees C to 25 degrees C. It is noted that W-doping in the process of reducing the transition temperature, alters the local structure and also increases room temperature carrier concentration. (c) 2016 Author(s).

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(Ga, Gd, As) film was fabricated by the mass-analyzed dual ion-beam epitaxy system with the energy of 1000 eV at room temperature. There was no new peak found except GaAs substrate peaks (0 0 2) and (0 0 4) by X-ray diffraction. Rocking curves were measured for symmetric (0 0 4) reflections to further yield the lattice mismatch information by employing double-crystal X-ray diffraction. The element distributions vary so much due to the ion dose difference from AES depth profiles. The sample surface morphology indicates oxidizing layer roughness is also relative to the Gd ion dose, which leads to islandlike feature appearing on the high-dose sample. One sample shows ferromagnetic behavior at room temperature. (C) 2003 Elsevier B.V. All rights reserved.

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Neste trabalho, os efeitos de um campo magnético oblíquo externo no modelo de Gross- Neveu (2+1)-dimensional, que inclui as componentes paralela e perpendicular do campo em relação ao sistema, são estudados no contexto da simetria quiral e discreta do modelo. Nosso principal interesse está nos efeitos deste campo sobre o diagrama de fase do sistema, onde também incluímos os efeitos combinados de temperatura e potencial químico. Os diagramas de fase são obtidos através do potencial efetivo a 1 loop para o modelo, derivado em primeira ordem na expansão 1=N. Transições de fase relevantes que podem ser estudadas através deste modelo são, por exemplo, metal-isolante em matéria condensada e na teoria quântica de campos de férmions planares em geral. A relação entre a transição de fase com quebra da simetria quiral e discreta e o surgimento de um gap (ou a presença de um valor esperado no vácuo do campo escalar diferente de zero), como função do campo magnético oblíquo, é analisada em detalhes.

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We demonstrate that the Mott metal-insulator transition (MIT) in single crystalline VO(2) nanowires is strongly mediated by surface stress as a consequence of the high surface area to volume ratio of individual nanowires. Further, we show that the stress-induced antiferromagnetic Mott insulating phase is critical in controlling the spatial extent and distribution of the insulating monoclinic and metallic rutile phases as well as the electrical characteristics of the Mott transition. This affords an understanding of the relationship between the structural phase transition and the Mott MIT.

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In the field of flat panel displays, the current leading technology is the Active Matrix liquid Crystal Display; this uses a-Si:H based thin film transistors (TFTs) as the switching element in each pixel. However, under gate bias a-Si:H TFTs suffer from instability, as is evidenced by a shift in the gate threshold voltage. The shift in the gate threshold voltage is generally measured from the gate transfer characteristics, after subjecting the TFT to prolonged gate bias. However, a major drawback of this measurement method is that it cannot distinguish whether the shift is caused by the change in the midgap states in the a-Si:H channel or by charge trapping in the gate insulator. In view of this, we have developed a capacitance-voltage (C-V) method to measure the shift in threshold voltage. We employ Metal-Insulator-Semiconductor (MIS) structures to investigate the threshold voltage shift as they are simpler to fabricate than TFTs. We have investigated a large of number Metal/a-Si:H/Si3N4/Si+n structures using our C-V technique. From, the C-V data for the MIS structures, we have found that the relationship between the thermal energy and threshold voltage shift is similar to that reported by Wehrspohn et. al in a-Si:H TFTs (J Appl. Phys, 144, 87, 2000). The a-Si:H and Si3N4 layers were grown using the radio-frequency plasma-enhanced chemical vapour deposition technique.

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Picosecond pulsed laser (10.4 ps, 1064 nm, 5 and 50 kHz) patterning studies were performed, of PEDOT:PSS thin films of varying thickness deposited by spin coating on glass substrates, by ablating the films or by changing locally by laser irradiation the optical and electrical properties of the polymer. From a detailed observation of the morphology of single pulse ablated holes on the surfaces of the films, in combination with simple calculations, it is concluded that photomechanical ablation is the likely ablation mechanism of the films. The single pulse ablation thresholds were measured equal to 0.13-0.18 J/cm 2 for films with thicknesses in the region of ∼100-600 nm. The implications on ablation line patterning of the films using different fluences, scanning speeds and pulse repetition rates, were investigated systematically. Laser irradiation of the films before ablation induces a metal-insulator transition of the polymer because of the formation of charge localization due to a possible creation of molecular disorder in the polymer and shortening of its conjugation length. © 2010 Elsevier B.V. All rights reserved.

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CaCu3Ti(4-x)Nb(x)O(12) (x = 0, 0.01, 0.08, 0.2) ceramics were fabricated by a conventional solid-state reaction method. The ceramics showed the body-centered cubic structure without any foreign phases and the grain size decreases with Nb doping. Two Debye-type relaxations were observed for the Nb-doped samples at low frequency and high frequency, respectively. The complex electric modulus analysis revealed that the surface layer, grains and grain boundaries contributed to the dielectric constant. The low-frequency dielectric constant relative to the surface layer decreased to a minimum and then increased with the dc bias voltage at 100 Hz, which were well explained in terms of a model containing two metal oxide semiconductors in series, confirming the surface layer in the ceramics. The shift voltage V-B corresponding to the minimal capacitance increased with increase of the composition x. (C) 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

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This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

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The magnetic semiconductor GdxSi1-x was prepared by low-energy dual ion-beam epitaxy. GdxSi1-x shows excellent magnetic properties at room temperature. A high magnetic moment of 10 mu(B) per Gd atom is observed. The high atomic magnetic moment is interpreted as being a result of the RKKY mechanism. The indirect exchange interaction between ions is strong at large distances due to the low state density of the carriers in the magnetic semiconductor.

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The hybrid integrated photonic switch and not logic gate based on the integration of a GaAs VCSEL (Vertical Cavity Surface Emitting Lasers) and a MISS (Metal-Insulator-Semiconductor Switches) device are reported. The GaAs VCSEL is fabricated by selective etching and selective oxidation. The Ultra-Thin semi-Insulating layer (UTI) of the GaAs MISS is formed by using oxidation of A1As that is grown by MBE. The accurate control of UTI and the processing compatibility between VCSEL and MISS are solved by this procedure. Ifa VCSEL is connected in series with a MISS, the integrated device can be used as a photonic switch, or a light amplifier. A low switching power (10 mu W) and a good on-off ratio (17 dB contrast) have been achieved. If they are connected in parallel, they perform a photonic NOT gate operation.

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This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.