On-Chip Clock Network Skew Measurement using Sub-Sampling

We present a technique for an all-digital on-chip delay measurement system to measure the skews in a clock distribution network. It uses the principle of sub-sampling. Measurements from a prototype fabricated in a 65 nm industrial process, indicate the ability to measure delays with a resolution of 0.5ps and a DNL of 1.2 ps.

7Li Spin-flip satellites in the EPR sectra of NH3+ -doped LiKSO4

EPR spectra of lithium potassium sulfate doped with NH3+ have been recorded at 9.05 GHz. A pair of satellites can be seen symmetrically situated on either side of the main lines. The separation of the satellite lines from the main line corresponds to the 7Li NMR frequency. The distance of the interacting 7Li nucleus from the unpaired electron in NH3+ is estimated to be 3.29 Å.

Influence of tool rake angle on the quality of pure magnesium chip-consolidated product

Chips were produced by orthogonal Cutting of cast pure magnesium billet with three different tool rake angles viz., -15 degrees, -5 degrees and +15 degrees on a lathe. Chip consolidation by solid state recycling technique involved cold compaction followed by hot extrusion. The extruded products were characterized for microstructure and mechanical properties. Chip-consolidated products from -15 degrees rake angle tools showed 19% increase in tensile strength, 60% reduction ingrain size and 12% increase in hardness compared to +15 degrees rake chip-consolidated product indicating better chip bonding and grain refinement. Microstructure of the fracture specimen Supports the abovefinding. On the overall, the present work high lights the importance of tool take angle in determining the quality of the chip-consolidated products. (C) 2009 Elsevier B.V. All rights reserved.

Power Optimal Network-on-Chip Interconnect Design

A large part of today's multi-core chips is interconnect. Increasing communication complexity has made essential new strategies for interconnects, such as Network on Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Techniques to reduce interconnect power have thus become a necessity. In this paper, we present a design methodology that gives values of bus width for interconnect links, frequency of operation for routers, in Network on Chip scenario that satisfy required throughput and dissipate minimal switching power. We develop closed form analytical expressions for the power dissipation, with bus width and frequency as variables and then use Lagrange multiplier method to arrive at the optimal values. We present a 4 port router in 90 nm technology library as case study. The results obtained from analysis are discussed.

Generic Routing Rules and a Scalable Access Enhancement for the Network-on-Chip RECONNECT

RECONNECT is a Network-on-Chip using a honeycomb topology. In this paper we focus on properties of general rules applicable to a variety of routing algorithms for the NoC which take into account the missing links of the honeycomb topology when compared to a mesh. We also extend the original proposal [5] and show a method to insert and extract data to and from the network. Access Routers at the boundary of the execution fabric establish connections to multiple periphery modules and create a torus to decrease the node distances. Our approach is scalable and ensures homogeneity among the compute elements in the NoC. We synthesized and evaluated the proposed enhancement in terms of power dissipation and area. Our results indicate that the impact of necessary alterations to the fabric is negligible and effects the data transfer between the fabric and the periphery only marginally.

Two-dimensional NMR spectroscopy of connected transitions by linear combination of flip angle dependent cosy: An alternative scheme for E.COSY

An alternative pulse scheme which simplifies and improves the recently proposed P.E.COSY experiment is suggested for the retention of connected or unconnected transitions in a coupled spin system. An important feature of the proposed pulse scheme is the improved phase characteristics of the diagonal peaks. A comparison of various experiments designed for this purpose, namely COSY-45, E.COSY, P.E.COSY and the present scheme (A.E.COSY), is also presented. The suppression of unconnected transitions and the measurement of scalar coupling constants and their relative signs are illustrated from A.E.COSY spectra of 2,3-dibromopropionic acid and 2-(2-thienyl)pyridine.

Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper we introduce a new energy-efficient fault-tolerant CMP architecture known as Redundant Execution using Critical Value Forwarding (RECVF). RECVF is based on two observations: (i) forwarding critical instruction results from the leading to the trailing core enables the latter to execute faster, and (ii) this speedup can be exploited to reduce energy consumption by operating the trailing core at a lower voltage-frequency level. Our evaluation shows that RECVF consumes 37% less energy than conventional dual modular redundant (DMR) execution of a program. It consumes only 1.26 times the energy of a non-fault-tolerant baseline and has a performance overhead of just 1.2%.

A portable battery-operated chip thermocycler based on induction heating

A microchip thermocycler, fabricated from silicon and Pyrex #7740 glass, is described. Usual resistive heating has been replaced by induction heating, leading to much simpler fabrication steps. Heating and cooling rates of 6.5 and 4.2 degreesC/s, respectively have been achieved, by optimising the heater dimensions and heating frequency (similar to200 kHz). Four devices are mounted on a heater, resulting in low power consumption (similar to 1.4 W per device on the average). Using simple on-off electronic temperature control, a temperature stability within -0.2 degreesC is achieved. Features such as induction heating, good temperature control, battery operation, and low power consumption make the device suitable for portable applications, particularly in polymerase chain reaction (PCR) systems. (C) 2002 Elsevier Science B.V. All rights reserved.

On the importance of backbone loop and peptide flip in the Walker sequence in F-1-ATPase action

The Walker sequence, GXXXXGKT, present in all the six subunits of F-1-ATPase exists in a folded form, known as phosphate-binding loop (P-loop). Analysis of the Ramachandran angles showed only small RMS deviation between the nucleotide-bound and nucleotide-free forms. This indicated a good overlap of the backbone loops. The catalytic beta-subunits (chains D, E and F) showed significant changes in the Ramachandran angles and the side chain torsion angles, but not the structural alpha-subunits (chains A, B and C). Most striking among these are the changes associated with Val160 and Gly161 corresponding to a flip in the peptide unit between them when a nucleotide is bound (chains D or F compared to nucleotide-free chain E). The conformational analysis further revealed a hitherto unnoticed hydrogen bond between amide-N of the flipped Gly161 and terminal phosphate-O of the nucleotide. This assigns a role for this conserved amino acid, otherwise ignored, of making an unusual direct interaction between the peptide backbone of the enzyme protein and the incoming nucleotide substrate. Significance of this interaction is enhanced, as it is limited only to the catalytic subunits, and also likely to involve a mechanical rotation of bonds of the peptide unit. Hopefully this is part of the overall events that link the chemical hydrolysis of ATP with the mechanical rotation of this molecule, now famous as tiny molecular motor.

A System-C based Micro architectural Exploration Framework for Latency, Power and Performance Trade-offs of On-Chip Interconnection

We describe a System-C based framework we are developing, to explore the impact of various architectural and microarchitectural level parameters of the on-chip interconnection network elements on its power and performance. The framework enables one to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. We provide preliminary results of using this framework to study the power, latency and throughput of a 4x4 multi-core processing array using mesh, torus and folded torus, for two different communication patterns of dense and sparse linear algebra. The traffic consists of both Request-Response messages (mimicing cache accesses)and One-Way messages. We find that the average latency can be reduced by increasing the pipeline depth, as it enables higher link frequencies. We also find that there exists an optimum degree of pipelining which minimizes energy-delay product.

Power Efficient Redundant Execution for Chip Multiprocessor

This paper describes the design of a power efficient microarchitecture for transient fault detection in chip multiprocessors (CMPs) We introduce a new per-core dynamic voltage and frequency scaling (DVFS) algorithm for our architecture that significantly reduces power dissipation for redundant execution with a minimal performance overhead. Using cycle accurate simulation combined with a simple first order power model, we estimate that our architecture reduces dynamic power dissipation in the redundant core by an mean value of 79% and a maximum of 85% with an associated mean performance overhead of only 1:2%