Process-variation resilient and voltage-scalable dct architecture for robust low-power computing

In this paper, we present a novel discrete cosine transform (DCT) architecture that allows aggressive voltage scaling for low-power dissipation, even under process parameter variations with minimal overhead as opposed to existing techniques. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors appear only from the long paths that are designed to be less contributive to output quality. The proposed architecture allows a graceful degradation in the peak SNR (PSNR) under aggressive voltage scaling as well as extreme process variations. Results show that even under large process variations (±3σ around mean threshold voltage) and aggressive supply voltage scaling (at 0.88 V, while the nominal voltage is 1.2 V for a 90-nm technology), there is a gradual degradation of image quality with considerable power savings (71% at PSNR of 23.4 dB) for the proposed architecture, when compared to existing implementations in a 90-nm process technology. © 2006 IEEE.

Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking

In this paper, we explore various arithmetic units for possible use in high-speed, high-yield ALUs operated at scaled supply voltage with adaptive clock stretching. We demonstrate that careful logic optimization of the existing arithmetic units (to create hybrid units) indeed make them further amenable to supply voltage scaling. Such hybrid units result from mixing right amount of fast arithmetic into the slower ones. Simulations on different hybrid adder and multipliers in BPTM 70 nm technology show 18%-50% improvements in power compared to standard adders with only 2%-8% increase in die-area at iso-yield. These optimized datapath units can be used to construct voltage scalable robust ALUs that can operate at high clock frequency with minimal performance degradation due to occasional clock stretching. © 2009 IEEE.

Significance Driven Computation: A Voltage-Scalable, Variation-Aware, Quality-Tuning Motion Estimator

In this paper we present a design methodology for algorithm/architecture co-design of a voltage-scalable, process variation aware motion estimator based on significance driven computation. The fundamental premise of our approach lies in the fact that all computations are not equally significant in shaping the output response of video systems. We use a statistical technique to intelligently identify these significant/not-so-significant computations at the algorithmic level and subsequently change the underlying architecture such that the significant computations are computed in an error free manner under voltage over-scaling. Furthermore, our design includes an adaptive quality compensation (AQC) block which "tunes" the algorithm and architecture depending on the magnitude of voltage over-scaling and severity of process variations. Simulation results show average power savings of similar to 33% for the proposed architecture when compared to conventional implementation in the 90 nm CMOS technology. The maximum output quality loss in terms of Peak Signal to Noise Ratio (PSNR) was similar to 1 dB without incurring any throughput penalty.

Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the "less-crucial" computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system-logic and memory-and spans multiple layers of design hierarchy-algorithm, architecture and circuit. The design methodology when applied to a multimedia subsystem shows large power benefits ( up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.

Spatially-resolved mapping of history-dependent coupled electrochemical and electronical behaviors of electroresistive NiO

Bias-induced oxygen ion dynamics underpins a broad spectrum of electroresistive and memristive phenomena in oxide materials. Although widely studied by device-level and local voltage-current spectroscopies, the relationship between electroresistive phenomena, local electrochemical behaviors, and microstructures remains elusive. Here, the interplay between history-dependent electronic transport and electrochemical phenomena in a NiO single crystalline thin film with a number of well-defined defect types is explored on the nanometer scale using an atomic force microscopy-based technique. A variety of electrochemically-active regions were observed and spatially resolved relationship between the electronic and electrochemical phenomena was revealed. The regions with pronounced electroresistive activity were further correlated with defects identified by scanning transmission electron microscopy. Using fully coupled mechanical-electrochemical modeling, we illustrate that the spatial distribution of strain plays an important role in electrochemical and electroresistive phenomena. These studies illustrate an approach for simultaneous mapping of the electronic and ionic transport on a single defective structure level such as dislocations or interfaces, and pave the way for creating libraries of defect-specific electrochemical responses.

Analysis of voltage source converter-based high-voltage direct current under DC line-to-earth fault

DC line faults on high-voltage direct current (HVDC) systems utilising voltage source converters (VSCs) are a major issue for multi-terminal HVDC systems in which complete isolation of the faulted system is not a viable option. Of these faults, single line-to-earth faults are the most common fault scenario. To better understand the system under such faults, this study analyses the behaviour of HVDC systems based on both conventional two-level converter and multilevel modular converter technology, experiencing a permanent line-to-earth fault. Operation of the proposed system under two different earthing configurations of converter side AC transformer earthed with converter unearthed, and both converter and AC transformer unearthed, was analysed and simulated, with particular attention paid to the converter operation. It was observed that the development of potential earth loops within the system as a result of DC line-to-earth faults leads to substantial overcurrent and results in oscillations depending on the earthing configuration.

Power Modeling and Capping for Heterogeneous ARM/FPGA SoCs

Low-power processors and accelerators that were originally designed for the embedded systems market are emerging as building blocks for servers. Power capping has been actively explored as a technique to reduce the energy footprint of high-performance processors. The opportunities and limitations of power capping on the new low-power processor and accelerator ecosystem are less understood. This paper presents an efficient power capping and management infrastructure for heterogeneous SoCs based on hybrid ARM/FPGA designs. The infrastructure coordinates dynamic voltage and frequency scaling with task allocation on a customised Linux system for the Xilinx Zynq SoC. We present a compiler-assisted power model to guide voltage and frequency scaling, in conjunction with workload allocation between the ARM cores and the FPGA, under given power caps. The model achieves less than 5% estimation bias to mean power consumption. In an FFT case study, the proposed power capping schemes achieve on average 97.5% of the performance of the optimal execution and match the optimal execution in 87.5% of the cases, while always meeting power constraints.

Fair charging strategies for EVs connected to a low-voltage distribution network

The development of smart grid technologies and appropriate charging strategies are key to accommodating large numbers of Electric Vehicles (EV) charging on the grid. In this paper a general framework is presented for formulating the EV charging optimization problem and three different charging strategies are investigated and compared from the perspective of charging fairness while taking into account power system constraints. Two strategies are based on distributed algorithms, namely, Additive Increase and Multiplicative Decrease (AIMD), and Distributed Price-Feedback (DPF), while the third is an ideal centralized solution used to benchmark performance. The algorithms are evaluated using a simulation of a typical residential low voltage distribution network with 50% EV penetration. © 2013 IEEE.

Investigation of AIMD based charging strategies for EVs connected to a low-voltage distribution network

In this paper we consider charging strategies that mitigate the impact of domestic charging of EVs on low-voltage distribution networks and which seek to reduce peak power by responding to time-ofday pricing. The strategies are based on the distributed Additive Increase and Multiplicative Decrease (AIMD) charging algorithms proposed in [5]. The strategies are evaluated using simulations conducted on a custom OpenDSS-Matlab platform for a typical low voltage residential feeder network. Results show that by using AIMD based smart charging 50% EV penetration can be accommodated on our test network, compared to only 10% with uncontrolled charging, without needing to reinforce existing network infrastructure. © Springer-Verlag Berlin Heidelberg 2013.

On-off based charging strategies for EVs connected to a Low Voltage distributon network

The development of appropriate Electric Vehicle (EV) charging strategies has been identified as an effective way to accommodate an increasing number of EVs on Low Voltage (LV) distribution networks. Most research studies to date assume that future charging facilities will be capable of regulating charge rates continuously, while very few papers consider the more realistic situation of EV chargers that support only on-off charging functionality. In this work, a distributed charging algorithm applicable to on-off based charging systems is presented. Then, a modified version of the algorithm is proposed to incorporate real power system constraints. Both algorithms are compared with uncontrolled and centralized charging strategies from the perspective of both utilities and customers. © 2013 IEEE.

Barrier characteristics of PtSi/p-Si schottky diodes as determined from I-V-T measurements

The current-voltage-temperature characteristics of PtSi/p-Si Schottky barrier diodes were measured in the temperature range 60-115 K. Deviation of the ideality factor from unity below 80 K may be modelled using the so-called T-0 parameter with T-0 = 18 K. It is also shown that the curvature in the Richardson plots may be remedied by using the flatband rather than the zero-bias saturation current density. Physically, the departure from ideality is interpreted in terms of an inhomogeneous Schottky contact. Here we determine a mean barrier height at T = 0 K, phi(b)(-0) = 223 mV, with an (assumed) Gaussian distribution of standard deviation sigma(phi) = 12.5 mV. These data are correlated with the zero-bias barrier height, phi(j)(0) = 192 mV (at T = 90 K), the photoresponse barrier height, phi(ph) = 205 mV, and the flatband barrier height, phi(fb) = 214 mV. Finally, the temperature coefficient of the flatband barrier was found to be -0.121 mV K-1, which is approximately equal to 1/2(dE(g)(i)/dT), thus suggesting that the Fermi level at the interface is pinned to the middle of the band gap.

Attentional bias to food-related visual cues: is there a role in obesity?

The incentive sensitisation model of obesity suggests that modification of the dopaminergic associated reward systems in the brain may result in increased awareness of food-related visual cues present in the current food environment. Having a heightened awareness of these visual food cues may impact on food choices and eating behaviours with those being most aware of or demonstrating greater attention to food-related stimuli potentially being at greater risk of overeating and subsequent weight gain. To date, research related to attentional responses to visual food cues has been both limited and conflicting. Such inconsistent findings may in part be explained by the use of different methodological approaches to measure attentional bias and the impact of other factors such as hunger levels, energy density of visual food cues and individual eating style traits that may influence visual attention to food-related cues outside of weight status alone. This review examines the various methodologies employed to measure attentional bias with a particular focus on the role that attentional processing of food-related visual cues may have in obesity. Based on the findings of this review, it appears that it may be too early to clarify the role visual attention to food-related cues may have in obesity. Results however highlight the importance of considering the most appropriate methodology to use when measuring attentional bias and the characteristics of the study populations targeted while interpreting results to date and in designing future studies.

In and out of home care decisions: The influence of confirmation bias in developing decision supportive reasoning

The aims of this study were to identify the themes Social Workers regard as important in supporting decisions to remove children from, or return them to, the care of their parents. To further elicit underlying hypotheses that are discernible in interpretation of evidence. A case study, comprising a two-part vignette with a questionnaire, recorded demographic information, child welfare attitudes and risk assessments, using scales derived from standardised instruments, was completed by 202 Social Workers in Northern Ireland. There were two manipulated variables, mother’s attitude to removal and child’s attitude to reunification2 years later. In this paper we use data derived from respondents’ qualitative comments explaining their reasoning for in and out of home care decisions. Some 60.9% of respondent’s chose the parental care option at part one, with 94% choosing to have the child remain in foster care at part two. The manipulated variables were found to have no significant statistical effect. However, three underlying hypotheses were found to underpin decisions; (a)child rescue, (b) kinship defence and (c) a hedged position on calculation of risk subject to further assessment. Reasoning strategies utilised by social workers to support their decision making suggest that they tend to selectively interpret information either positively or negatively to support pre-existing underlying hypotheses. This finding is in keeping with the literature on ‘confirmation bias.’ The research further draws attention to the need to incorporate open questions in quantitative studies, to help guard against surface reading of data, which often does not ‘speak for itself.’

The Equiprobability Bias from a Mathematical and Psychological Perspective

The equiprobability bias (EB) is a tendency to believe that every process in which randomness is involved corresponds to a fair distribution, with equal probabilities for any possible outcome. The EB is known to affect both children and adults, and to increase with probability education. Because it results in probability errors resistant to pedagogical interventions, it has been described as a deep misconception about randomness: the erroneous belief that randomness implies uniformity. In the present paper, we show that the EB is actually not the result of a conceptual error about the definition of randomness. On the contrary, the mathematical theory of randomness does imply uniformity. However, the EB is still a bias, because people tend to assume uniformity even in the case of events that are not random. The pervasiveness of the EB reveals a paradox: The combination of random processes is not necessarily random. The link between the EB and this paradox is discussed, and suggestions are made regarding educational design to overcome difficulties encountered by students as a consequence of the EB.