Fast Sorting on a Distributed-Memory Architecture

We consider the often-studied problem of sorting, for a parallel computer. Given an input array distributed evenly over p processors, the task is to compute the sorted output array, also distributed over the p processors. Many existing algorithms take the approach of approximately load-balancing the output, leaving each processor with Θ(n/p) elements. However, in many cases, approximate load-balancing leads to inefficiencies in both the sorting itself and in further uses of the data after sorting. We provide a deterministic parallel sorting algorithm that uses parallel selection to produce any output distribution exactly, particularly one that is perfectly load-balanced. Furthermore, when using a comparison sort, this algorithm is 1-optimal in both computation and communication. We provide an empirical study that illustrates the efficiency of exact data splitting, and shows an improvement over two sample sort algorithms.

Memory Hierarchy Hardware-Software Co-design in Embedded Systems

The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious resources in embedded systems. Moreover, embedded systems have multiple design objectives such as performance, energy consumption, and area, etc. Customizing the memory hierarchy for specific applications is a very important way to take full advantage of limited resources to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They separate the application optimization from the memory hierarchy architecture design, which tend to result in local-optimal solutions. In traditional Hardware-Software co-design methodologies, much of the work has focused on utilizing reconfigurable logic to partition the computation. However, utilizing reconfigurable logic to perform the memory hierarchy design is seldom addressed. In this paper, we propose a new framework for designing memory hierarchy for embedded systems. The framework will take advantage of the flexible reconfigurable logic to customize the memory hierarchy for specific applications. It combines the application optimization and memory hierarchy design together to obtain a global-optimal solution. Using the framework, we performed a case study to design a new software-controlled instruction memory that showed promising potential.

Memory Usage Inference for Object-Oriented Programs

We present a type-based approach to statically derive symbolic closed-form formulae that characterize the bounds of heap memory usages of programs written in object-oriented languages. Given a program with size and alias annotations, our inference system will compute the amount of memory required by the methods to execute successfully as well as the amount of memory released when methods return. The obtained analysis results are useful for networked devices with limited computational resources as well as embedded software.

Failure-Oblivious Computing and Boundless Memory Blocks

Memory errors are a common cause of incorrect software execution and security vulnerabilities. We have developed two new techniques that help software continue to execute successfully through memory errors: failure-oblivious computing and boundless memory blocks. The foundation of both techniques is a compiler that generates code that checks accesses via pointers to detect out of bounds accesses. Instead of terminating or throwing an exception, the generated code takes another action that keeps the program executing without memory corruption. Failure-oblivious code simply discards invalid writes and manufactures values to return for invalid reads, enabling the program to continue its normal execution path. Code that implements boundless memory blocks stores invalid writes away in a hash table to return as the values for corresponding out of bounds reads. he net effect is to (conceptually) give each allocated memory block unbounded size and to eliminate out of bounds accesses as a programming error. We have implemented both techniques and acquired several widely used open source servers (Apache, Sendmail, Pine, Mutt, and Midnight Commander).With standard compilers, all of these servers are vulnerable to buffer overflow attacks as documented at security tracking web sites. Both failure-oblivious computing and boundless memory blocks eliminate these security vulnerabilities (as well as other memory errors). Our results show that our compiler enables the servers to execute successfully through buffer overflow attacks to continue to correctly service user requests without security vulnerabilities.

Sexual orientation and spatial memory

Resumen tomado de la publicaci??n

Attention, memory and verbal learning and their relation to schizotypal traits in unaffected parents of schizophrenic patients

The main objective of this ex post facto study is to compare the differences in cognitive functions and their relation to schizotypal personality traits between a group of unaffected parents of schizophrenic patients and a control group. A total of 52 unaffected biological parents of schizophrenic patients and 52 unaffected parents of unaffected subjects were assessed in measures of attention (Continuous Performance Test- Identical Pairs Version, CPT-IP), memory and verbal learning (California Verbal Learning Test, CVLT) as well as schizotypal personality traits (Oxford-Liverpool Inventory of Feelings and Experiences, O-LIFE). The parents of the patients with schizophrenia differ from the parents of the control group in omission errors on the Continuous Performance Test- Identical Pairs, on a measure of recall and on two contrast measures of the California Verbal Learning Test. The associations between neuropsychological variables and schizotpyal traits are of a low magnitude. There is no defined pattern of the relationship between cognitive measures and schizotypal traits

El papel de la memoria de trabajo en el cálculo mental un cuarto de siglo después de Hitch = The role of working memory in mental arithmetic a quarter of century after Hitch

Desde que Hitch (1978) publicó el primer estudio sobre el rol de la memoria de trabajo en el cálculo han ido aumentando las investigaciones en este campo. Muchos trabajos han estudiado un único subsistema, pero nuestro objetivo es identificar qué subsistema de la memoria de trabajo (bucle fonológico, agenda viso-espacial o ejecutivo central) está más implicado en el cálculo mental. Para ello hemos realizado un estudio correlacional en el que hemos administrado dos pruebas aritméticas y nueve pruebas de la “Bateria de Test de Memòria de Treball” de Pickering, Baqués y Gathercole (1999) a una muestra de 94 niños españoles de 7-8 años. Nuestros resultados indican que el bucle fonológico y sobretodo el ejecutivo central inciden de forma estadísticamente significativa en el rendimiento aritmético

Short-term storage and mental speed account for the relationship between working memory and fluid intelligence. 'El almacenamiento a corto plazo y la velocidad mental dan cuenta de la relaci??n entre memoria de trabajo e inteligencia fluida'

Resumen tomado de la publicaci??n

Executive function and memory in patients with relapsing-remitting multiple sclerosis. 'Funci??n ejecutiva y memoria en pacientes con esclerosis m??ltiple recurrente-remitente'

Resumen tomado de la publicaci??n

Effects of memory load on visual search

Resumen tomado de la publicaci??n

Memory, revision and exam techniques

University of Southampton, Dyslexia Services have developed a range of academic study skills resources available to download. This resource supports revision and techniques for use in examinations.

COMP6043 Conducting Interviews

Slides which take students through the interview process, mediated through the presentation of published papers which use interview data

Interviews And Focus Groups: Purpose Paradigms Protocols and Pragmatics

Introduction to interview data, how it is used and how and why it might be collected

IRP Poster - Side-effects in Software Transactional Memory

Poster for IRP project 'Side-effects in Software Transactional Memory: Extending Deuce with TwilightSTM'