Technology and the architecture of markets: re-configuring the Canadian equity market

This paper examines the relation between technical possibilities, liberal logics, and the concrete reconfiguration of markets. It focuses on the enrolling of innovations in communication and information technologies into the markets traditionally dominated by stock exchanges. With the development of capacities to trade on-screen, the power of incumbent market makers has been challenged as a less stable array of competing quasi-public and private marketplaces emerges. Developing a case study of the Toronto Stock Exchange, I argue that narrative emphasis on the performative power of sociotechnical innovations, the deterritorialisation of financial relations, and the erosion of state capacities needs qualification. A case is made for the importance of developing an understanding of: the spaces of encounter between emerging social technologies and property rights, rules of exchange, and structures of governance; and the interplay of orderings of different institutional composition and spatial reach in the reconfiguration of market architectures. Only then can a better grasp be gained of the evolving dynamics between making markets, the regulatory powers of the state, and their delimitations.

A VLSI Architecture for Variable Block Size Video Motion Estimation

With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding, particularly in the area of variable block size video motion estimation (VBSME), are increasing. In this paper, we propose a new one-dimensional (1-D) very large-scale integration architecture for full-search VBSME (FSVBSME). The VBS sum of absolute differences (SAD) computation is performed by re-using the results of smaller sub-block computations. These are distributed and combined by incorporating a shuffling mechanism within each processing element. Whereas a conventional 1-D architecture can process only one motion vector (MV), this new architecture can process up to 41 MV sub-blocks (within a macroblock) in the same number of clock cycles.

Generic Architecture and Semiconductor Intellectual Property Cores for Avanced Encryption Standard Cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.