A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

A Novel Power Supply Solution of a Passive RFID Transponder

This paper presents a power supply solution for fully integrated passive radio-frequency identification(RFID) transponder IC,which has been implemented in 0.35μm CMOS technology with embedded EEPROM from Chartered Semiconductor.The proposed AC/DC and DC/DC charge pumps can generate stable output for RFID applications with quite low power dissipation and extremely high pumping efficiency.An analytical model of the voltage multiplier,comparison with other charge pumps,simulation results,and chip testing results are presented.

A High Speed, 12-Channel Parallel, Monolithic Integrated CMOS OEIC Receiver

The design and fabrication of a high speed, 12-channel monolithic integrated CMOS optoelectronic integrated circuit(OEIC) receiver are reported.Each channel of the receiver consists of a photodetector,a transimpedance amplifier,and a post-amplifier.The double photodiode structure speeds up the receiver but hinders responsivity.The adoption of active inductors in the TIA circuit extends the-3dB bandwidth to a higher level.The receiver has been realized in a CSMC 0.6μm standard CMOS process.The measured results show that a single channel of the receiver is able to work at bit rates of 0.8～1.4Gb/s. Altogether, the 12-channel OEIC receiver chip can be operated at 15Gb/s.

High Speed VCSEL-Based Parallel Optical Transmission Modules

Design and fabrication of a parallel optical transmitter are reported. The optimized 12 channel parallel optical transmitter,with each channel＇s data rate up to 3Gbit/s,is designed, assembled, and measured. A top-emitting 850nm vertical cavity surface emitting laser（VCSEL） array is adopted as the light source,and the VCSEL chip is directly wire bonded to a 12 channel driver IC. The outputs of the VCSEL array are directly butt coupled into a 12 channel fiber array. Small form factor pluggable （SFP） packaging technology is used in the module to support hot pluggable in application. The performance results of the module are demonstrated. At an operating current of 8mA, an eye diagram at 3Gbit/s is achieved with an optical output of more than 1mW.

A 12bit 300MHz Current-Steering CMOS D/A Converter

The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs, trading-off between the precision, speed, and size of the chip. In order to ensure the linearity of the DAC, a double Centro symmetric current matrix is designed by the Q2 random walk strategy. To achieve better dynamic performance, a latch is added in front of the current switch to change the input signal, such as its optimal cross-point and voltage level. For a 12bit resolution,the converter reaches an update rate of 300MHz.

Design,Fabrication,and Testing of Single-Side Alignment of 16×0.8nm Arrayed-Waveguide Grating

A novel design of 100GHz-spaced 16channel arrayed-waveguide grating (AWG) based on silica-on-silicon chip is reported.AWG is achieved by adding a Y-branch to the AWG and arranging the input/output channel in a neat row,so the whole configuration can be aligned and packaged using only one fiber-array.This configuration can decrease the device's size,enlarge the minimum radius of curvature,save time on polishing and alignment,and reduce the chip's fabrication cost.

Integrated electroabsorption-modulated DFB laser by using an improved butt-joint method

An improved butt coupling method is used to fabricate an electroabsorption modulator (EAM) monolithically integrated with a distributed feedback (DFB) laser. The obtained electroabsorption-modulated laser (EML) chip with the traditional shallow ridge exhibits very low threshold current of 12 mA, output power of more than 8 mW, and static extinction ratio of -7 dB at the applied bias voltage from 0.5 to -2.0 V.

16-channel 0.35 mu m CMOS/VCSEL optoelectronic devices

We report some investigations on vertical cavity surface emitting laser (VCSEL) arrays and VCSEL based optoelectronic smart photonic multiple chip modules (MCM), consisting of 1 x 16 vertical cavity surface emitting laser array and 16-channel lasers driver 0.35 mum CMOS circuit. The hybrid integrated multiple chip modules based on VCSEL operate at more than 2GHz in -3dB frequency bandwidth.

Hybrid CMOS/VCSEL optoelectronic modules

We report some investigations on vertical cavity surface emitting laser (VCSEL) arrays and VCSEL based optoelectronic smart photonic multiple chip modules (MCM), consisting of 1x16 vertical cavity surface emitting laser array and 16-channel lasers driver 0.35 Pin CMOS circuit. The hybrid integrated multiple chip modules based on VCSEL operate at more than 2GHz in -3dB frequency bandwidth.

Low power design in 100 MHz embedded SRAM

Low power design method is used in a 100MHz embedded SRAM. The embedded SRAM used in a FFT chip is divided into 16 blocks. Two-level decoders are used and only one block can be selected at one time by tristate control circuits, while other blocks are set stand-by. The SRAM cell has been optimized and the cell area has been minimized at the same time.

Scan test in 18x8 bits Booth Coding-Wallace Tree multiplier

Scan test can be inserted around hard IP cores that have not been designed with DFT approaches. An 18x18 bits Booth Coding-Wallace Tree multiplier has been designed with full custom approach with 0.61 m CMOS technology. When we reuse the multiplier in another chip, scan chain has been inserted around it to increase the fault coverage. After scan insertion, the multiplier needs 4.7% more areas and 24.4% more delay time, while the fault coverage reaches to 95%.

Intelligent control of avalanched photodiode to get optimal state

To improve the sensitivity of our laser radar system, we provided a set of control method for APDs (Avalanched Photodiodes) based on single-chip computer together with the circuits dealing with noise and temperature. It adjusts the voltages intelligently and maintains the APD's optimal working status.

Native oxided AlAs current blocking layer for AIGaInP high brightness light emitting diodes

Native Oxide AlAs layer were employed to block the current injection from the tup anode. The luminous intensity exceeded 75 mcd of the LED chip with native oxide AlAs layer sandwiched 5 mu m AlGaAs current spreading layer under 20 mA current injection. Electrical and optical properties the LED chip and plastically sealed lamp were measured. Aging of the LED chip and lamp were performed under 70 degrees C and room temperature, Experiment results shown that there is no apparent effect of the native oxided AlAs layer and the process on the reliability of the LED devices.

Multiple quantum well self electro-optic effect devices for optoelectronic smart pixels

The investigations on GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays for optoelectronic smart pixels are reported. The hybrid integration of GaAs/AlGaAs multiple quantum well devices flip-chip bonding directly over 1 mu m silicon CMOS circuits are demonstrated. The GaAs/AlGaAs multiple quantum well devices are designed for 850nm operation. The measurement results under applied biases show the good optoelectronic characteristics of elements in SEED arrays. The 4x4 optoelectronic crossbar structure consisting of hybrid CMOS-SEED smart pixels have been designed, which could be potentially used in optical interconnects for multiple processors.

Influence of processing temperature on microstructure and microhardness of copper subjected to high-pressure torsion

Cu samples were subjected to high-pressure torsion (HPT) with up to 6 turns at room temperature (RT) and liquid nitrogen temperature (LNT), respectively. The effects of temperature on grain refinement and microhardness variation were investigated. For the samples after HPT processing at RT, the grain size reduced from 43 mu m to 265 nm, and the Vickers microhardness increased from HV52 to HV140. However, for the samples after HPT processing at LNT, the value of microhardness reached its maximum of HV150 near the center of the sample and it decreased to HV80 at the periphery region. Microstructure observations revealed that HPT straining at LNT induced lamellar structures with thickness less than 100 nm appearing near the central region of the sample, but further deformation induced an inhomogeneous distribution of grain sizes, with submicrometer-sized grains embedded inside micrometer-sized grains. The submicrometer-sized grains with high dislocation density indicated their nonequilibrium nature. On the contrary, the micrometer-sized grains were nearly free of dislocation, without obvious deformation trace remaining in them. These images demonstrated that the appearance of micrometer-sized grains is the result of abnormal grain growth of the deformed fine grains.