Optical properties of semiconductor quantum wires

This thesis presents theoretical investigations of the sub band structure and optical properties of semiconductor quantum wires. For the subband structure, we employ multiband effective-mass theory and the effective bond-orbital model both of which fully account for the band mixing and material anisotropy. We also treat the structure geometry in detail taking account of such effects as the compositional grading across material interfaces. Based on the subband structure, we calculate optical properties of quantum-wire structures. A recuring theme is the cross-over from one- to ~wo-dimensional behavior in these structures. This complicated behavior procludes the application of simple theoretical models to obtain the electronic structure. In particular, we calculate laser properties of quantum wires grown in V-grooves and find enhanced performance compared with quantum-well lasers. We also investigate optical anisotropy in quantum-wire arrays and propose an electro-optic device based on such structures.

Reduced graphene oxide wrapped Cu2O supported on C3N4: An efficient visible light responsive semiconductor photocatalyst

Herein, Cu 2O spheres were prepared and encapsulated with reduced graphene oxide (rGO). The Cu 2O–rGO–C3N4 composite covered the whole solar spectrum with significant absorption intensity. rGO wrapped Cu 2O loading caused a red shift in the absorption with respect to considering the absorption of bare C3N4. The photoluminescence study confirms that rGO exploited as an electron transport layer at the interface of Cu 2O and C3N4 heterojunction. Utmost, ∼2 fold synergistic effect was achieved with Cu 2O–rGO–C3N4 for the photocatalytic reduction of 4-nitrophenol to 4-aminophenol in comparison with Cu 2O–rGO and C3N4. The Cu 2O–rGO–C3N4 photocatalyst was reused for four times without loss in its activity.

Interface state mapping in a Schottky barrier of the organic semiconductor terrylene

In this work we quantitatively map interface states in energy in a Schottky barrier between aluminum and the vacuum sublimed organic semiconductor terrylene. The density map of these interface states was extracted from the, admittance spectroscopy data. They revealed an interface state density of 2 x 10(12). cm(-2)eV(-1) close to the valence band which decreases slightly towards midgap. Additional do measurements show that the semiconductor bulk activation energy is 0.33 eV which may correspond to an acceptor level. (C) 2002 Elsevier Science B.V. All rights reserved.

Carrier momentum relaxation in highly doped polar semiconductors and semiconductor heterostructures

Highly doped polar semiconductors are essential components of today’s semiconductor industry. Most strikingly, transistors in modern electronic devices are polar semiconductor heterostructures. It is important to thoroughly understand carrier transport in such structures. In doped polar semiconductors, collective excitations of the carriers (plasmons) and the atoms (polar phonons) couple. These coupled collective excitations affect the electrical conductivity, here quantified through the carrier mobility. In scattering events, the carriers and the coupled collective modes transfer momentum between each other. Carrier momentum transferred to polar phonons can be lost to other phonons through anharmonic decay, resulting in a finite carrier mobility. The plasmons do not have a decay mechanism which transfers carrier momentum irretrievably. Hence, carrier-plasmon scattering results in infinite carrier mobility. Momentum relaxation due to either carrier–plasmon scattering or carrier–polar-phonon scattering alone are well understood. However, only this thesis manages to treat momentum relaxation due to both scattering mechanisms on an equal footing, enabling us to properly calculate the mobility limited by carrier–coupled plasmon–polar phonon scattering. We achieved this by solving the coupled Boltzmann equations for the carriers and the collective excitations, focusing on the “drag” term and on the anharmonic decay process of the collective modes. Our approach uses dielectric functions to describe both the carrier-collective mode scattering and the decay of the collective modes. We applied our method to bulk polar semiconductors and heterostructures where various polar dielectrics surround a semiconducting monolayer of MoS2, where taking plasmons into account can increase the mobility by up to a factor 15 for certain parameters. This screening effect is up to 85% higher than if calculated with previous methods. To conclude, our approach provides insight into the momentum relaxation mechanism for carrier–coupled collective mode scattering, and better tools for calculating the screened polar phonon and interface polar phonon limited mobility.

Engineering interfacial silicon dioxide for improved metal-insulator-semiconductor silicon photoanode water splitting performance

Silicon photoanodes protected by atomic layer deposited (ALD) TiO2 show promise as components of water splitting devices that may enable the large-scale production of solar fuels and chemicals. Minimizing the resistance of the oxide corrosion protection layer is essential for fabricating efficient devices with good fill factor. Recent literature reports have shown that the interfacial SiO2 layer, interposed between the protective ALD-TiO2 and the Si anode, acts as a tunnel oxide that limits hole conduction from the photoabsorbing substrate to the surface oxygen evolution catalyst. Herein, we report a significant reduction of bilayer resistance, achieved by forming stable, ultrathin (<1.3 nm) SiO2 layers, allowing fabrication of water splitting photoanodes with hole conductances near the maximum achievable with the given catalyst and Si substrate. Three methods for controlling the SiO2 interlayer thickness on the Si(100) surface for ALD-TiO2 protected anodes were employed: (1) TiO2 deposition directly on an HF-etched Si(100) surface, (2) TiO2 deposition after SiO2 atomic layer deposition on an HF-etched Si(100) surface, and (3) oxygen scavenging, post-TiO2 deposition to decompose the SiO2 layer using a Ti overlayer. Each of these methods provides a progressively superior means of reliably thinning the interfacial SiO2 layer, enabling the fabrication of efficient and stable water oxidation silicon anodes.

Micro-structure differences in kaolinite suspensions

SEM observations of the aqueous suspensions of kaolinite from Birdwood (South Australia) and Georgia (USA) show noticeable differences in number of physical behaviour which has been explained by different microstructure constitution.. Birdwood kaolinite dispersion gels are observed at very low solid loadings in comparison with Georgia KGa-1 kaolinite dispersions which remain fluid at higher solids loading. To explain this behaviour, the specific particle interactions of Birdwood kaolinite, different from interaction in Georgia kaolinite have been proposed. These interactions may be brought about by the presence of nano-bubbles on clay crystal edges and may force clay particles to aggregate by bubble coalescence. This explains the predominance of stair step edge-edge like (EE) contacts in suspension of Birdwood kaolinite. Such EE linked particles build long strings that form a spacious cell structure. Hydrocarbon contamination of colloidal kaolinite particles and low aspect ratio are discussed as possible explanations of this unusual behaviour of Birdwood kaolinite. In Georgia KGa-1 kaolinite dispersions instead of EE contact between platelets displayed in Birdwood kaolinite, most particles have edge to face (EF) contacts building a cardhouse structure. Such an arrangement is much less voluminous in comparison with the Birdwood kaolinite cellular honeycomb structure observed previously in smectite aqueous suspensions. Such structural characteristics of KGa-1 kaolinite particles enable higher solid volume fractions pulps to form before significantly networked gel consistency is attained.

A new multilevel converter configuration for high power and high quality applications

The Queensland University of Technology (QUT) allows the presentation of theses for the Degree of Doctor of Philosophy in the format of published or submitted papers, where such papers have been published, accepted or submitted during the period of candidature. This thesis is composed of ten published /submitted papers and book chapters of which nine have been published and one is under review. This project is financially supported by an Australian Research Council (ARC) Discovery Grant with the aim of investigating multilevel topologies for high quality and high power applications, with specific emphasis on renewable energy systems. The rapid evolution of renewable energy within the last several years has resulted in the design of efficient power converters suitable for medium and high-power applications such as wind turbine and photovoltaic (PV) systems. Today, the industrial trend is moving away from heavy and bulky passive components to power converter systems that use more and more semiconductor elements controlled by powerful processor systems. However, it is hard to connect the traditional converters to the high and medium voltage grids, as a single power switch cannot stand at high voltage. For these reasons, a new family of multilevel inverters has appeared as a solution for working with higher voltage levels. Besides this important feature, multilevel converters have the capability to generate stepped waveforms. Consequently, in comparison with conventional two-level inverters, they present lower switching losses, lower voltage stress across loads, lower electromagnetic interference (EMI) and higher quality output waveforms. These properties enable the connection of renewable energy sources directly to the grid without using expensive, bulky, heavy line transformers. Additionally, they minimize the size of the passive filter and increase the durability of electrical devices. However, multilevel converters have only been utilised in very particular applications, mainly due to the structural limitations, high cost and complexity of the multilevel converter system and control. New developments in the fields of power semiconductor switches and processors will favor the multilevel converters for many other fields of application. The main application for the multilevel converter presented in this work is the front-end power converter in renewable energy systems. Diode-clamped and cascade converters are the most common type of multilevel converters widely used in different renewable energy system applications. However, some drawbacks – such as capacitor voltage imbalance, number of components, and complexity of the control system – still exist, and these are investigated in the framework of this thesis. Various simulations using software simulation tools are undertaken and are used to study different cases. The feasibility of the developments is underlined with a series of experimental results. This thesis is divided into two main sections. The first section focuses on solving the capacitor voltage imbalance for a wide range of applications, and on decreasing the complexity of the control strategy on the inverter side. The idea of using sharing switches at the output structure of the DC-DC front-end converters is proposed to balance the series DC link capacitors. A new family of multioutput DC-DC converters is proposed for renewable energy systems connected to the DC link voltage of diode-clamped converters. The main objective of this type of converter is the sharing of the total output voltage into several series voltage levels using sharing switches. This solves the problems associated with capacitor voltage imbalance in diode-clamped multilevel converters. These converters adjust the variable and unregulated DC voltage generated by renewable energy systems (such as PV) to the desirable series multiple voltage levels at the inverter DC side. A multi-output boost (MOB) converter, with one inductor and series output voltage, is presented. This converter is suitable for renewable energy systems based on diode-clamped converters because it boosts the low output voltage and provides the series capacitor at the output side. A simple control strategy using cross voltage control with internal current loop is presented to obtain the desired voltage levels at the output voltage. The proposed topology and control strategy are validated by simulation and hardware results. Using the idea of voltage sharing switches, the circuit structure of different topologies of multi-output DC-DC converters – or multi-output voltage sharing (MOVS) converters – have been proposed. In order to verify the feasibility of this topology and its application, steady state and dynamic analyses have been carried out. Simulation and experiments using the proposed control strategy have verified the mathematical analysis. The second part of this thesis addresses the second problem of multilevel converters: the need to improve their quality with minimum cost and complexity. This is related to utilising asymmetrical multilevel topologies instead of conventional multilevel converters; this can increase the quality of output waveforms with a minimum number of components. It also allows for a reduction in the cost and complexity of systems while maintaining the same output quality, or for an increase in the quality while maintaining the same cost and complexity. Therefore, the asymmetrical configuration for two common types of multilevel converters – diode-clamped and cascade converters – is investigated. Also, as well as addressing the maximisation of the output voltage resolution, some technical issues – such as adjacent switching vectors – should be taken into account in asymmetrical multilevel configurations to keep the total harmonic distortion (THD) and switching losses to a minimum. Thus, the asymmetrical diode-clamped converter is proposed. An appropriate asymmetrical DC link arrangement is presented for four-level diode-clamped converters by keeping adjacent switching vectors. In this way, five-level inverter performance is achieved for the same level of complexity of the four-level inverter. Dealing with the capacitor voltage imbalance problem in asymmetrical diodeclamped converters has inspired the proposal for two different DC-DC topologies with a suitable control strategy. A Triple-Output Boost (TOB) converter and a Boost 3-Output Voltage Sharing (Boost-3OVS) converter connected to the four-level diode-clamped converter are proposed to arrange the proposed asymmetrical DC link for the high modulation indices and unity power factor. Cascade converters have shown their abilities and strengths in medium and high power applications. Using asymmetrical H-bridge inverters, more voltage levels can be generated in output voltage with the same number of components as the symmetrical converters. The concept of cascading multilevel H-bridge cells is used to propose a fifteen-level cascade inverter using a four-level H-bridge symmetrical diode-clamped converter, cascaded with classical two-level Hbridge inverters. A DC voltage ratio of cells is presented to obtain maximum voltage levels on output voltage, with adjacent switching vectors between all possible voltage levels; this can minimize the switching losses. This structure can save five isolated DC sources and twelve switches in comparison to conventional cascade converters with series two-level H bridge inverters. To increase the quality in presented hybrid topology with minimum number of components, a new cascade inverter is verified by cascading an asymmetrical four-level H-bridge diode-clamped inverter. An inverter with nineteen-level performance was achieved. This synthesizes more voltage levels with lower voltage and current THD, rather than using a symmetrical diode-clamped inverter with the same configuration and equivalent number of power components. Two different predictive current control methods for the switching states selection are proposed to minimise either losses or THD of voltage in hybrid converters. High voltage spikes at switching time in experimental results and investigation of a diode-clamped inverter structure raised another problem associated with high-level high voltage multilevel converters. Power switching components with fast switching, combined with hard switched-converters, produce high di/dt during turn off time. Thus, stray inductance of interconnections becomes an important issue and raises overvoltage and EMI issues correlated to the number of components. Planar busbar is a good candidate to reduce interconnection inductance in high power inverters compared with cables. The effect of different transient current loops on busbar physical structure of the high-voltage highlevel diode-clamped converters is highlighted. Design considerations of proper planar busbar are also presented to optimise the overall design of diode-clamped converters.

A modified quality control method for manufacturing process in mask industry

Masks are widely used in different industries, for example, traditional metal industry, hospitals or semiconductor industry. Quality is a critical issue in mask industry as it is related to public health and safety. Traditional quality practices for manufacturing process have some limitations in implementing them in mask industries. This paper aims to investigate the suitability of Six Sigma quality control method for the manufacturing process in the mask industry to provide high quality products, enhancing the process capacity, reducing the defects and the returned goods arising in a selected mask manufacturing company. This paper suggests that modifications necessary in Six Sigma method for effective implementation in mask industry.

Carbon nanotube synthesis from germanium nanoparticles on patterned substrates

Controlled synthesis of carbon nanotubes (CNTs) is highly desirable for nanoelectronic applications. To date, metallic catalyst particles have been deemed unavoidable for the nucleation and growth of any kind of CNTs. Ordered arrays of nanotubes have been obtained by controlled deposition of the metallic catalyst particles. However, the presence of metal species mixed with the CNTs represents a shortcoming for most electronic applications, as metal particles are incompatible with silicon semiconductor technology. In the present paper we report on a metal-catalyst-free synthesis of CNTs, obtained through Ge nanoparticles on a Si(001) surface patterned by nanoindentation. By using acetylene as the carbon feed gas in a low-pressure Chemical Vapor Deposition (CVD) system, multi-walled carbon nanotubes (MWNT) have been observed to arise from the smallest Ge islands. The CNTs and the Ge three-dimensional structures have been analysed by SEM, EDX and AFM in order to assess their elemental features and properties. EDX and SEM results allow confirmation of the absence of any metallic contamination on the surface, indicating that the origin of the CNT growth is due to the Ge nanocrystals.