Comparison of virus dispersal and aerosolization by different hand-drying devices

Background World Health Organization and EU hand hygiene guidelines state that if electric hand dryers are used, they should not aerosolize pathogens. Previous studies have investigated the dispersal by different hand-drying devices of chemical indicators, fungi and bacteria on the hands. This study assessed the aerosolization and dispersal of virus on the hands to determine any differences between hand-drying devices in their potential to contaminate other occupants of public washrooms and the washroom environment. Methods A suspension of MS2, an Escherichia coli bacteriophage virus, was used to artificially contaminate the hands of participants prior to using three different hand-drying devices: jet air dryer, warm air dryer, paper towel dispenser. Virus was detected by plaque formation on agar plates layered with the host bacterium. Vertical dispersal of virus was assessed at a fixed distance (0.4 m) and over a range of different heights (0.0 – 1.8 m) from the floor. Horizontal dispersal was assessed at different distances of up to three metres from the hand-drying devices. Virus aerosolization and dispersal was also assessed at different times up to 15 minutes after use by means of air sampling at two distances (0.1 and 1.0 m) and at a distance behind and offset from each of the hand-drying devices. Results Over a range of heights, the jet air dryer was shown to produce over 60 times greater vertical dispersal of virus from the hands than a warm air dryer and over 1300 times greater than paper towels; the maximum being detected between 0.6 and 1.2 metres from the floor. Horizontal dispersal of virus by the jet air dryer was over 20 times greater than a warm air dryer and over 190 times greater than paper towels; virus being detected at distances of up to three metres. Air sampling at three different positions from the hand-drying devices 15 minutes after use showed that the jet air dryer produced over 50-times greater viral contamination of the air than a warm air dryer and over 110-times greater than paper towels. Conclusions Due to their high air speed, jet air dryers aerosolize and disperse more virus over a range of heights, greater distances, and for longer times than other hand drying devices. If hands are inadequately washed, they have a greater potential to contaminate other occupants of a public washroom and the washroom environment. Main messages: Jet air dryers with claimed air speeds of over 600 kph have a greater potential than warm air dryers or paper towels to aerosolize and disperse viruses on the hands of users. The choice of hand-drying device should be carefully considered. Jet air dryers may increase the risk of transmission of human viruses, such as norovirus, particularly if hand washing is inadequate.

An FPGA based decimation filter processor design for real-time continuous-time Σ−Δ modulator performance measurement and evaluation

This paper reports on a Field Programmable Gate Array (FPGA) implementation as well as prototyping for real-time testing of a low complexity high efficiency decimation filter processor which is deployed in conjunction with a custom built low-power jitter insensitive Continuous Time (CT) Sigma-Delta (Σ-Δ) Modulator to measure and assess its performance. The CT Σ-Δ modulator/decimation filter cascade can be used in integrated all-digital microphone interfaces for a variety of applications including mobile phone handsets, wireless handsets as well as other applications requiring all-digital microphones. The work reported here concentrates on the design and implementation as well as prototyping on a Xilinx Spartan 3 FPGA development system and real-time testing of the decimation processing part deploying All-Pass based structures to process the bit stream coming from CT Σ-Δ modulator hence measuring in real-time and fully assessing the modulator's performance.

Receptor MIMO em FPGA baseado no esquema de Alamouti

A oferta de serviços baseados em comunicações sem fios tem vindo a crescer exponencialmente na última década. Cada vez mais são exigidas maiores taxas de transmissão assim como uma melhor QoS, sem comprometer a potência de transmissão ou argura de banda disponível. A tecnologia MIMO consegue oferecer um aumento da capacidade destes sistemas sem requerer aumento da largura de banda ou da potência transmitida. O trabalho desenvolvido nesta dissertação consistiu no estudo dos sistemas MIMO, caracterizados pela utilização de múltiplas antenas para transmitir e receber a informação. Com um sistema deste tipo consegue-se obter um ganho de diversidade espacial utilizando códigos espaço-temporais, que exploram simultaneamente o domínio espacial e o domínio do tempo. Nesta dissertação é dado especial ênfase à codificação por blocos no espaço-tempo de Alamouti, a qual será implementada em FPGA, nomeadamente a parte de recepção. Esta implementação é efectuada para uma configuração de antenas 2x1, utilizando vírgula flutuante e para três tipos de modulação: BPSK, QPSK e 16-QAM. Por fim será analisada a relação entre a precisão alcançada na representação numérica dos resultados e os recursos consumidos pela FPGA. Com a arquitectura adoptada conseguem se obter taxas de transferência na ordem dos 29,141 Msimb/s (sem pipelines) a 262,674 Msimb/s (com pipelines), para a modulação BPSK.

Design of a Multiband Full-Rate Ultra-Wideband Receiver in FPGA

MultiBand OFDM (MB-OFDM) UWB [1] is a short-range promising wireless technology for high data rate communications up to 480 Mbps. In this paper, we have designed and implemented in an Virtex-6 FPGA an MB-OFDM UWB receiver for the highest data rate of 480 Mbps. To test the system, we have also implemented an MB-OFDM transmitter and an AWGN generator in VHDL and determined the bit error rates at the receiver running in an FPGA.

Projecto de uma câmara em rede em FPGA

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Sistema de multiprocessamento para simulação de N-corpos em FPGA

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Many-core approach to 2D-DCT calculation using an FPGA

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A high-rate mimo receiver in an FPGA

This paper describes the hardware implementation of a High-Rate MIMO Receiver in an FPGA for three modulations, namely BPSK, QPSK and 16-QAM based on the Alamouti scheme. The implementation with 16-QAM achieves more than 1.6 Gbps with 66% of the resources of a medium-sized Virtex-4 FPGA. This results indicate that the Alamouti scheme is a good design option for hardware implementation of a high-rate MIMO receiver. Also, using an FPGA, the modulation can be dynamically changed on demand.

Demux devices based on A-SiC:H

In this paper we present results about the functioning of a multilayered a-SiC:H heterostructure as a device for wavelength-division demultiplexing of optical signals. The device is composed of two stacked p-i-n photodiodes, both optimized for the selective collection of photogenerated carriers. Band gap engineering was used to adjust the photogeneration and recombination rates profiles of the intrinsic absorber regions of each photodiode to short and long wavelength absorption and carrier collection in the visible spectrum. The photocurrent signal using different input optical channels was analyzed at reverse and forward bias and under steady state illumination. This photocurrent is used as an input for a demux algorithm based on the voltage controlled sensitivity of the device. The device functioning is explained with results obtained by numerical simulation of the device, which permit an insight to the internal electric configuration of the double heterojunction.These results address the explanation of the device functioning in the frequency domain to a wavelength tunable photocapacitance due to the accumulation of space charge localized at the internal junction. The existence of a direct relation between the experimentally observed capacitive effects of the double diode and the quality of the semiconductor materials used to form the internal junction is highlighted.

FPGA implementation of IEEE 802.15.3C receiver

This paper presents the implementation of the OFDM demodulator and the Viterbi decoder, proposed as part of a wireless High Definition video receiver to be integrated in an FPGA. These blocks were implemented in a Xilinx Virtex-6 FPGA. The complete system was previously modeled and simulated using MATLAB/Simulink to extract importante hardware characteristics for the FPGA implementation.

Peers' evaluation of a reconfigurable IEEE1451.0-compliant and FPGA-based weblab

It is already more than 10 years that weblabs are seen as important resources to provide the experimental work required in engineering education. Several weblabs have been applied in engineering courses, but there are still unsolved problems related to the development of their infrastructures. For solving some of those problems, it was implemented a weblab with a reconfigurable infrastructure compliant with the IEEE1451.0 Std. and supported by Field Programmable Gate Array (FPGA) technology. This paper presents the referred weblab, and provides and analyses a set of researchers' opinions about the implemented infrastructure, and the adopted methodology for the conduction of real experiments.

Educational application of remote experimentation for mobile devices

In this article the authors describe the application development RExMobile and the importance of remote experimentation via mobile devices, especially smartphones simple, beyond the space provided for this application in education. The article deals the creation, software and hardware that provide an interactive and dynamic way to attract more students to use these experiments remote, serving as support to teachers to science teaching from its initial series. The ease and availability of smartphones, even these students of basic education, permits the reach of new users and in different places. Thus, the practice of remote experimentation in mobile devices enables new spaces for access and interaction. Are used for developing software free or low cost, HTML5 and jQuery Mobile framework, that enable the creation of pages compatible with different mobile operating systems such as iOS, Android, Windows Phone, some Symbian, among others. Also are demonstrated patterns layouts that allow greater accessibility.

FPGA-based weblab infrastructures guidelines and a prototype implementation example

Recent trends show an increasing number of weblabs, implemented at universities and schools, supporting practical training in technical courses and providing the ability to remotely conduct experiments. However, their implementation is typically based on individual architectures, unable of being reconfigured with different instruments/modules usually required by every experiment. In this paper, we discuss practical guidelines for implementing reconfigurable weblabs that support both local and remote control interfaces. The underlying infrastructure is based on reconfigurable, low-cost, FPGA-based boards supporting several peripherals that are used for the local interface. The remote interface is powered by a module capable of communicating with an Ethernet based network and that can either correspond to an internal core of the FPGA or an external device. These two approaches are discussed in the paper, followed by a practical implementation example.

A self-healing real-time system based on run-time self-reconfiguration

The new generations of SRAM-based FPGA (field programmable gate array) devices are the preferred choice for the implementation of reconfigurable computing platforms intended to accelerate processing in real-time systems. However, FPGA's vulnerability to hard and soft errors is a major weakness to robust configurable system design. In this paper, a novel built-in self-healing (BISH) methodology, based on run-time self-reconfiguration, is proposed. A soft microprocessor core implemented in the FPGA is responsible for the management and execution of all the BISH procedures. Fault detection and diagnosis is followed by repairing actions, taking advantage of the dynamic reconfiguration features offered by new FPGA families. Meanwhile, modular redundancy assures that the system still works correctly

JPEG decoder implementation on FPGA using dynamic partial reconfiguration

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