FPGA implementation of IEEE 802.15.3C receiver
| Data(s) |
07/09/2015
07/09/2015
2012
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|---|---|
| Resumo |
This paper presents the implementation of the OFDM demodulator and the Viterbi decoder, proposed as part of a wireless High Definition video receiver to be integrated in an FPGA. These blocks were implemented in a Xilinx Virtex-6 FPGA. The complete system was previously modeled and simulated using MATLAB/Simulink to extract importante hardware characteristics for the FPGA implementation. |
| Identificador |
VÉSTIAS, Mário Pereira; SARMENTO, Helena – FPGA implementation of IEEE 802.15.3C receiver. In IEEE 16Th International Symposium on Consumer Electronics (ISCE). IEEE, 2012. ISBN: 978-1-4673-1356-8 978-1-4673-1356-8 |
| Idioma(s) |
eng |
| Publicador |
IEEE |
| Direitos |
closedAccess |
| Tipo |
article conferenceObject |
