959 resultados para Concurrent object- oriented Petri nets (CO-OPN)
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Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores
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Trabalho de Projeto apresentado ao Instituto de Contabilidade e Administração do Porto para a obtenção do grau de Mestre em Auditoria, sob orientação do Dr. Rodrigo Carvalho e co-orientação do Major de Artilharia António Rabaço
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Relatório de Estágio submetidoà Escola Superior de Teatro e Cinemapara cumprimento dos requisitos necessários à obtenção do grau de Mestre em Artes Performativas- especialização em Teatro-Música
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The development of an algorithm for the construction of auxiliary projection nets (conform, equivalent and orthographic), in the equatorial and polar versions, is presented. The algorithm for the drawing of the "IGAREA 220" counting net (ALYES & MENDES, 1972), is also presented. Those algorithms are the base of STEGRAPH program (vers. 2.0), for MS-DOS computers, which has other applications.
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Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.
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Relatório de Estágio submetido à Escola Superior de Teatro e Cinema para cumprimento dos requisitos necessários à obtenção do grau de Mestre em Artes Performativas – especialização em Teatro-‐Música.
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In this work, alpha-Co(OH)(2) is electrodeposited onto carbon nanofoam forming a composite electrode operating in a potential window of 2 V in aqueous medium. Prior to electrodeposition, the carbon nanofoam substrate is subjected to a functionalization process, which leads to an increase of about 40% in its specific capacitance value. Formation of cobalt hydroxide clusters onto the functionalized carbon nanofoam by pulse electrodeposition further enhances the specific capacitance of the electrode. The combination of these factors with an enlarged working potential window, results in a material with specific capacitance close to 300 F g(-1) at current density of 1 A g(-1), considering the total mass loading of the composite. This suggests the potential application of the prepared composites in high energy density electrochemical supercapacitors. (c) 2015 Elsevier B.V. All rights reserved.
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Trabalho de Projecto submetido à Escola Superior de Teatro e Cinema para cumprimento dos requisitos necessários à obtenção do grau de Mestre em Teatro – Especialização em Encenação.
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Cubic cobalt nitride films were grown onto different single crystalline substrates Al2O3 (0 0 0 1) and (1 1 View the MathML source 0), MgO (1 0 0) and (1 1 0) and TiO2 (1 0 0) and (1 1 0). The films display low atomic densities compared with the bulk material, are ferromagnetic and have metallic electrical conductivity. X-ray diffraction and X-ray absorption fine structure confirm the cubic structure of the films and with RBS results indicate that samples are not homogeneous at the microscopic scale, coexisting Co4+xN nitride with nitrogen rich regions. The magnetization of the films decreases with increase of the nitrogen content, variation that is shown to be due to the decrease of the cobalt density, and not to a decrease of the magnetic moment per cobalt ion. The films are crystalline with a nitrogen deficient stoichiometry and epitaxial with orientation determined by the substrate.
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The synthesis of nanocomposite materials combining titanate nanofibers (TNF) with nanocrystalline ZnS and Bi2S3 semiconductors is described in this work. The TNF were produced via hydrothermal synthesis and sensitized with the semiconductor nanoparticles, through a single-source precursor decomposition method. ZnS and Bi2S3 nanoparticles were successfully grown onto the TNF's surface and Bi2S3-ZnS/TNF nanocomposite materials with different layouts. The samples' photocatalytic performance was first evaluated through the production of the hydroxyl radical using terephthalic acid as probe molecule. All the tested samples show photocatalytic ability for the production of this oxidizing species. Afterwards, the samples were investigated for the removal of methylene blue. The nanocomposite materials with best adsorption ability were the ZnS/TNF and Bi2S3ZnS/TNF. The dye removal was systematically studied, and the most promising results were obtained considering a sequential combination of an adsorption-photocatalytic degradation process using the Bi2S3ZnS/TNF powder as a highly adsorbent and photocatalyst material. (C) 2015 Elsevier Ltd. All rights reserved.
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Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Electrotécnica e Computadores
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Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores
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Even though Software Transactional Memory (STM) is one of the most promising approaches to simplify concurrent programming, current STM implementations incur significant overheads that render them impractical for many real-sized programs. The key insight of this work is that we do not need to use the same costly barriers for all the memory managed by a real-sized application, if only a small fraction of the memory is under contention lightweight barriers may be used in this case. In this work, we propose a new solution based on an approach of adaptive object metadata (AOM) to promote the use of a fast path to access objects that are not under contention. We show that this approach is able to make the performance of an STM competitive with the best fine-grained lock-based approaches in some of the more challenging benchmarks. (C) 2015 Elsevier Inc. All rights reserved.
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Single processor architectures are unable to provide the required performance of high performance embedded systems. Parallel processing based on general-purpose processors can achieve these performances with a considerable increase of required resources. However, in many cases, simplified optimized parallel cores can be used instead of general-purpose processors achieving better performance at lower resource utilization. In this paper, we propose a configurable many-core architecture to serve as a co-processor for high-performance embedded computing on Field-Programmable Gate Arrays. The architecture consists of an array of configurable simple cores with support for floating-point operations interconnected with a configurable interconnection network. For each core it is possible to configure the size of the internal memory, the supported operations and number of interfacing ports. The architecture was tested in a ZYNQ-7020 FPGA in the execution of several parallel algorithms. The results show that the proposed many-core architecture achieves better performance than that achieved with a parallel generalpurpose processor and that up to 32 floating-point cores can be implemented in a ZYNQ-7020 SoC FPGA.
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Dissertação apresentada na Faculdade de Ciências e Tecnologias da Universidade Nova de Lisboa para a obtenção do Grau de Mestre em Engenharia Informática