Efficient analysis, design, and filter applications of EBG waveguide with periodic resonant loads

An efficient analysis and design of an electromagnetic-bandgap (EBG) waveguide with resonant loads is presented. Equivalent-circuit analysis is employed to demonstrate the differences between EBG waveguides with resonant and nonresonant loadings. As a result of the resonance, transmission zeros at finite frequencies emerge. The concept is demonstrated in E-plane waveguides. A generic fast and efficient formulation is presented, which starts from the generalized scattering matrix of the unit cell and derives the dispersion properties of the infinite structure. Both real and imaginary parts of the propagation constant are derived and discussed. The Floquet wavelength and impedance are also presented. The theoretical results are validated by comparison with simulations of a finite structure and experimental results. The application of the proposed EBG waveguide in the suppression of the spurious passband of a conventional E-plane filter is presented by experiment.

Design of asymmetrical RF and microwave bandpass filters by computer optimization

This paper presents an optimization-based approach to the design of asymmetrical filter structures having the maximum number of return- or insertion-loss ripples in the passband such as those based upon Chebyshev function prototypes. The proposed approach. has the following advantages over the general purpose optimization techniques adopted previously such as: less frequency sampling is required, optimization is carried out with respect to the Chebyshev (or minimax) criterion, the problem of local minima does not arise, and optimization is usually only required for the passband. When implemented around an accurate circuit simulation, the method can be used to include all the effects of discontinuities, junctions, fringing, etc. to reduce the amount of tuning required in the final filter. The design of asymmetrical ridged-waveguide bandpass filters is considered as an example. Measurements on a fabricated filter confirm the accuracy of the design procedure.

The effects of the specific adsorption of anion on the reactivity of the Ru(0001) surface towards CO adsorption and oxidation: in situ FTIRS studies

The dynamics of adsorption and oxidation of CO on Ru(0001) electrode in sulfuric acid solution have been studied using in situ FTIR spectroscopy under potential control and at open circuit, the latter at 20 and 55 degrees C. The in situ IR data show clearly that the bisulfate anion adsorbs on the Ru(0001) surface over the potential range from -200 mV to 350 mV (vs. Ag/AgCl) at 20 degrees C in the absence and presence of adsorbed CO; however, increasing the temperature to 55 degrees C and/ or increasing the concentration of dissolved O-2 reduces the bisulfate adsorption. The formation of surface (hydro-) oxide at higher potentials replaces the bisulfate adsorbates. Both linear (COL) and three-fold hollow bonded CO (COH) adsorbates were produced following CO adsorption at Ru(0001) in H2SO4, as was observed in our previous studies in HClO4. However, the amount of adsorbed CO observed in H2SO4 was ca. 10% less than that in HClO4; in addition, the COL and COH frequencies were higher in H2SO4, and the onset potential for COads oxidation 25 mV lower. These new results are interpreted in terms of a model in which the adsorbed bisulfate weakens the CO adlayer, allowing the active Ru oxide layer to form at lower potentials. Significantly different results were observed at open circuit in H2SO4 compared both to the data under potential control and to our earlier data in HClO4, and these observations were rationalized in terms of the adsorbed HSO4- anions (pre-adsorbed at -200 mV) inhibiting the oxidation of the surface at open circuit (after stepping from the initial potential of -200 mV), as the latter was no longer driven by the imposed electrochemical potential but via chemical oxidation by trace dissolved O-2. Results from experiments at open circuit at 55 degrees C and using oxygen-saturated H2SO4 supported this model. The difference in Ru surface chemistry between imposed electrochemical control and chemical control has potential implications with respect to fuel cell electrocatalysis.

Electro-thermal theory of intermodulation distortion in lossy microwave components

An analytic formulation of dynamic electro-thermally induced nonlinearity is developed for a general resistive element, yielding a self-heating circuit model based on a fractional derivative. The model explains the 10 dB/decade slope of the intermodulation products observed in two-tone testing. Two-tone testing at 400 MHz of attenuators, microwave chip terminations, and coaxial terminations is reported with tone spacing ranging from 1 to 100 Hz.

Hierarchical synthesis of complex DSP functions on FPGAs

SoC systems are now being increasingly constructed using a hierarchy of subsystems or silicon Intellectual Property (IP) cores. The key challenge is to use these cores in a highly efficient manner which can be difficult as the internal core structure may not be known. A design methodology based on synthesizing hierarchical circuit descriptions is presented. The paper employs the MARS synthesis scheduling algorithm within the existing IRIS synthesis flow and details how it can be enhanced to allow for design exploration of IP cores. It is shown that by accessing parameterised expressions for the datapath latencies in the cores, highly efficient FPGA solutions can be achieved. Hardware sharing at both the hierarchical and flattened levels is explored for a normalized lattice filter and results are presented.

Rapid design of biorthogonal wavelet transforms

A rapid design methodology for biorthogonal wavelet transform cores has been developed based on a generic, scaleable architecture for wavelet filters. The architecture offers efficient hardware utilisation by combining the linear phase property of biorthogonal filters with decimation in a MAC-based implementation. The design has been captured in VHDL and parameterised in terms of wavelet type, data word length and coefficient word length. The control circuit is embedded within the cores and allows them to be cascaded without any interface glue logic for any desired level of decomposition. The design time to produce silicon layout of a biorthogonal wavelet system is typically less than a day. The silicon cores produced are comparable in area and performance to hand-crafted designs, The designs are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

Current transients in the small salient-pole alternator caused by sudden short-circuit and synchronisation events

Small salient-pole machines, in the range 30 kVA to 2 MVA, are often used in distributed generators, which in turn are likely to form the major constituent of power generation in power system islanding schemes or microgrids. In addition to power system faults, such as short-circuits, islanding contains an inherent risk of out-of-synchronism re-closure onto the main power system. To understand more fully the effect of these phenomena on a small salient-pole alternator, the armature and field currents from tests conducted on a 31.5 kVA machine are analysed. This study demonstrates that by resolving the voltage difference between the machine terminals and bus into direct and quadrature axis components, interesting properties of the transient currents are revealed. The presence of saliency and short time-constants cause intriguing differences between machine events such as out-of-phase synchronisations and sudden three-phase short-circuits.

Non-invasive VHF monitoring of low-temperature atmospheric pressure plasma

A real-time VHF swept frequency (20–300 MHz) reflectometry measurement for radio-frequency capacitive-coupled atmospheric pressure plasmas is described. The measurement is scalar, non-invasive and deployed on the main power line of the plasma chamber. The purpose of this VHF signal injection is to remotely interrogate in real-time the frequency reflection properties of plasma. The information obtained is used for remote monitoring of high-value atmospheric plasma processing. Measurements are performed under varying gas feed (helium mixed with 0–2% oxygen) and power conditions (0–40 W) on two contrasting reactors. The first is a classical parallel-plate chamber driven at 16 MHz with well-defined electrical grounding but limited optical access and the second is a cross-field plasma jet driven at 13.56 MHz with open optical access but with poor electrical shielding of the driven electrode. The electrical measurements are modelled using a lumped element electrical circuit to provide an estimate of power dissipated in the plasma as a function of gas and applied power. The performances of both reactors are evaluated against each other. The scalar measurements reveal that 0.1% oxygen admixture in helium plasma can be detected. The equivalent electrical model indicates that the current density between the parallel-plate reactor is of the order of 8–20 mA cm-2 . This value is in accord with 0.03 A cm-2 values reported by Park et al (2001 J. Appl. Phys. 89 20–8). The current density of the cross-field plasma jet electrodes is found to be 20 times higher. When the cross-field plasma jet unshielded electrode area is factored into the current density estimation, the resultant current density agrees with the parallel-plate reactor. This indicates that the unshielded reactor radiates electromagnetic energy into free space and so acts as a plasma antenna.

A scalable packet sorting circuit for high-speed WFQ packet scheduling

A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano-circuit simulation. The FinFET used in this work is designed using careful engineering of source-drain extension, which simultaneously improves maximum frequency of oscillation f(max) because of lower gate to drain capacitance, and intrinsic gain A(V0) = g(m)/g(ds), due to lower output conductance g(ds). The framework for the ANN-based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I-d on drain-source V-ds and gate-source V-gs is derived by a simple two-layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low-noise amplifier. At low power (J(ds) similar to 10 mu A/mu m) improvement was observed in both third-order-intercept IIP3 (similar to 10 dBm) and intrinsic gain A(V0) (similar to 20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first-order to third-order derivative of I-d with respect to gate voltage and lower g(ds), in FinFET compared to bulk MOSFET. Copyright (C) 2009 John Wiley & Sons, Ltd.

Impact of gate-source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

In this work, we report on the significance of gate-source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (A(VO_OTA)) > 55 dB and unity gain frequency (f(T_OTA)) similar to 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in A(VO_OTA) and three fold enhancement in f(T_OTA) over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. A(VO_OTA) values exhibited by a DG MOSFET-based OTA are 1.3-1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. f(T_OTA) values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in A(VO_OTA) and f(T_OTA) highlights the usefulness of underlap channel architecture in improving gain-bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve 'idealized' DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/sigma) ratio of 3.2 and operated below a bias current (IBIAS) of 80 mu A demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.

Design of quantum-dot cellular automata circuits using cut-set retiming

As a potential alternative to CMOS technology, QCA provides an interesting paradigm in both communication and computation. However, QCAs unique four-phase clocking scheme and timing constraints present serious timing issues for interconnection and feedback. In this work, a cut-set retiming design procedure is proposed to resolve these QCA timing issues. The proposed design procedure can accommodate QCAs unique characteristics by performing delay-transfer and time-scaling to reallocate the existing delays so as to achieve efficient clocking zone assignment. Cut-set retiming makes it possible to effectively design relatively complex QCA circuits that include feedback. It utilizes the similar characteristics of synchronization, deep pipelines and local interconnections common to both QCA and systolic architectures. As a case study, a systolic Montgomery modular multiplier is designed to illustrate the procedure. Furthermore, a nonsystolic architecture, an S27 benchmark circuit, is designed and compared with previous designs. The comparison shows that the cut-set retiming method achieves a more efficient design, with a reduction of 22%, 44%, and 46% in terms of cell count, area, and latency, respectively.

Analysis and Design of Class-E3F and Transmission-Line Class-E3F2 Power Amplifiers

In this paper, analysis and synthesis approach for two new variants within the Class-EF power amplifier (PA) family is elaborated. These amplifiers are classified here as Class-E3 F2 and transmission-line (TL) Class-E3 F 2. The proposed circuits offer means to alleviate some of the major issues faced by existing topologies such as substantial power losses due to the parasitic resistance of the large inductor in the Class-EF load network and deviation from ideal Class-EF operation due to the effect of device output inductance at high frequencies. Both lumped-element and transmission-line load networks for the Class-E 3 F PA are described. The load networks of the Class-E3 F and TL Class-E 3 F2amplifier topologies developed in this paper simultaneously satisfy the Class-EF optimum impedance requirements at fundamental frequency, second, and third harmonics as well as simultaneously providing matching to the circuit optimum load resistance for any prescribed system load resistance. Optimum circuit component values are analytically derived and validated by harmonic balance simulations. Trade-offs between circuit figures of merit and component values with some practical limitations being considered are discussed. © 2010 IEEE.

Quantum circuits for spin and flavor degrees of freedom of quarks forming nucleons

We discuss the quantum-circuit realization of the state of a nucleon in the scope of simple simmetry groups. Explicit algorithms are presented for the preparation of the state of a neutron or a proton as resulting from the composition of their quark constituents. We estimate the computational resources required for such a simulation and design a photonic network for its implementation. Moreover, we highlight that current work on three-body interactions in lattices of interacting qubits, combined with the measurement-based paradigm for quantum information processing, may also be suitable for the implementation of these nucleonic spin states.