A phase Ib trial of Docetaxel, Carboplatin and Erlotinib in ovarian, fallopian tube and primary peritoneal cancers.

The safety and maximum tolerated dose (MTD) of erlotinib with docetaxel/carboplatin were assessed in patients with ovarian cancer. Chemonaive patients received intravenous docetaxel (75 mg m(-2)) and carboplatin (area under the curve 5) on day 1 of a 3-week cycle, and oral erlotinib at 50 (cohort 1), 100 (cohort 2a) or 75 mg day(-1) (cohort 2b) for up to six cycles. Dose-limiting toxicities were determined in cycle 1. Forty-five patients (median age 59 years) received treatment. Dose-limiting toxicities occurred in 1/5/5 patients (cohorts 1/2a/2b). The MTD of erlotinib in this regimen was determined to be 75 mg day(-1) (cohort 2b; the erlotinib dose was escalated to 100 mg day(-1) in 11 out of 19 patients from cycle 2 onwards). Neutropaenia was the predominant grade 3/4 haematological toxicity (85/100/95% respectively). Common non-haematological toxicities were diarrhoea, fatigue, nausea and rash. There were five complete and seven partial responses in 23 evaluable patients (52% response rate). Docetaxel/carboplatin had no measurable effect on erlotinib pharmacokinetics. In subsequent single-agent maintenance, erlotinib was given at 100-150 mg day(-1), with manageable toxicity, until tumour progression. Further investigation of erlotinib in epithelial ovarian carcinoma may be warranted, particularly as maintenance therapy

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

High tolerance to gate misalignment in low voltage gate-underlap double gate MOSFETs

.In this letter, we demonstrate for the first time that gate misalignment is not a critical limiting factor for low voltage operation in gate-underlap double gate (DG) devices. Our results show that underlap architecture significantly extends the tolerable limit of gate misalignment in 25 nm devices. DG MOSFETs with high degree of gate misalignment and optimal gate-underlap design can perform comparably or even better than self-aligned nonunderlap devices. Results show that spacer-to-straggle (s/sigma) ratio, a key design parameter for underlap devices, should be within the range of 2.3-3.0 to accommodate back gate misalignment. These results are very significant as the stringent process control requirements for achieving self-alignment in nanoscale planar DG MOSFETs are considerably relaxed